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Test Case Prioritization Using UML state chart diagram and End-User Priority 3rd

3rd International Conference on Computational Intelligence in Data Mining (ICCIDM)

作者： Panda, Namita Acharya, Arup Abhinna Bhuyan, Prachet Mohapatra, Durga Prasad KIIT Univ Sch Comp Engn Bhubaneswar 751024 India Natl Inst Technol Dept Comp Sci & Engn Rourkela 769008 India

ISBN: (纸本)9789811038747;9789811038730

The intangible behaviour of software has given rise to various challenges in the field of testing software. One of the major challenges is to efficiently carry out regression testing. Regression testing is performed to ensure that any modifications in one component of the software do not adversely affect the other components. But, the retesting of test cases during regression testing increases the testing time and leads to delayed delivery of the software product. In this paper, a dynamic model, i.e. UML state chart diagram, is used for system modelling. Further, the UML state chart diagram is converted into an intermediate representation, i.e. state chart Graph (SCG). The SCG is traversed to identify the affected nodes due to certain modification in the software. This information, about the affected nodes, is periodically stored in a historical data store across different versions of the software. Next time, when regression testing is carried out for any change, the stored data decides the pattern of frequently affected nodes for prioritizing the test cases and further it decides the criticality value (CV) of a test case. Along with this, to strengthen the prioritization the test sequence, two more criteria, i.e. priority set by the end-user for different functions and browsing history of the end-user, are also added up. This approach is found to be very efficient as we are able to model dynamic nature of applications, maintain a historical data store of the test cases and track the complete life of an object.

关键词： state chart diagram state chart graph Regression testing UML model Prioritization

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Generic Methodology for Formal Verification of UML Models

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DEFENCE SCIENCE JOURNAL 2022年第1期72卷 40-48页

作者： Kochaleema, K. H. Kumar, G. Santhosh Cochin Univ Sci & Technol Kochi 682022 Kerala India DRDO Naval Phys & Oceanog Lab Kochi 682021 Kerala India

This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation.

关键词： Formal verification Computational tree logic Linear temporal logic Property specification state chart diagram UML modelling

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A UML-based Approach towards Test Case Generation and Optimization

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KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS 2024年第3期18卷 633-652页

作者： Saleem, Shahid Malik, Saif U. R. Mehboob, Bilal Alroobaea, Roobaea Algarni, Sultan Baqasah, Abdullah M. Ahmad, Naveed Hasnain, Muhammad Lahore Leads Univ Fac Comp Sci Lahore Punjab Pakistan Cybernetica AS Tallinn Estonia Super Univ Dept Software Engn Lahore 54000 Pakistan Taif Univ Coll Comp & Informat Technol Dept Comp Sci POB 11099 Taif 21944 Saudi Arabia King Abdulaziz Univ KAU Fac Comp & Informat Technol Dept Informat Syst Jeddah 21589 Saudi Arabia Taif Univ Coll Comp & Informat Technol Dept Informat Technol Taif 21974 Saudi Arabia Natl Univ Comp & Emerging Sci Dept Software Engn POB 42230 Islamabad Pakistan

Software testing is an important phase as it ensures the software quality. The software testing process comprises of three steps: generation, execution, and evaluation of test cases. Literature claims the usage of single and multiple 'Unified Modeling Language' (UML) diagrams to generate test cases. Using multiple UML diagrams increases test case coverage. However, the existing approaches show limitations in test case generation from UML diagrams. Therefore, in this research study, we propose an approach to generate the test cases using UML state chart diagram (SCD), Activity diagram (AD), and Sequence diagram (SD). The proposed approach transforms UML diagrams into intermediate forms: SCD Graph, AD Graph, and SD Graph respectively. Furthermore, by integrating these three graphs, a System Testing Graph (STG) is formed. Finally, test cases are identified from STG by using a traversal algorithm such as Depth First Search (DFS) that is an optimization method. The results show that the proposed approach is better compared to existing approaches in terms of coverage and performance. Moreover, the generated test cases have the ability to detect faults at the unit level, integration, and system level testing.

关键词： Activity diagram state chart diagram Sequence diagram System Testing Graph Model Based Testing Test Case Generation

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Methodology for Integrating Computational Tree Logic Model Checking in Unified Modelling Language Artefacts: A Case Study of an Embedded Controller

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DEFENCE SCIENCE JOURNAL 2019年第1期69卷 58-64页

作者： Kochaleema, K. H. Santhoshkumar, G. DRDO Naval Phys & Oceanog Lab Kochi 682021 Kerala India Cochin Univ Sci & Technol Fac Technol Kochi 682022 Kerala India

A unified modelling language (UML) based formal verification methodology that can be easily integrated into an embedded system software development life cycle is suggested. The approach augments UML diagrams with formal models through an interfacing domain and adds semantics to these diagrams. The suggested methodology;commences from functional specification and use case modelling, selects the most critical behaviour where formal verification can add value to the development cycle, analyses the selected behaviour using UML state transition diagram, derives a state chart matrix from the same, and a high level language software translates the state chart matrix to a labelled transition system. Safety properties are derived from system specifications and are expressed as computation tree logic (CTL) formulae. CTL model-checking algorithm from the literature is used for model-checking. The applicability of the suggested approach is established using a safety critical embedded controller used for deployment and recovery of sensor structures from an airborne platform.

关键词： Unified modelling language state chart diagram state chart matrix Safety property specification Computational tree logic Formal verification

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Generating Testcases for Concurrent Systems Using UML state chart diagram

Generating Testcases for Concurrent Systems Using UML State ...

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International Conference on Advances in Information Technology and Mobile Communication (AIM 2011)

作者： Patnaik, Debashree Acharya, Arup Abhinna Mohapatra, Durga P. School of Computer Engineering KIIT University India Department of Computer Science and Engineering National Institute of Technology Rourkela India

ISBN: (纸本)9783642205729

Communication and concurrency are the major factors needed for the construction of a concurrent system: In concurrent environment systematic testing becomes a complex task. Generating test cases in concurrent environment is a difficult task because of arbitrary meddling of the concurrent thread. The interference of the concurrent thread may lead to a deadlock. In this paper we propose a methodology to generate the test cases for the conformance of deadlock in concurrent systems using UML state chart diagram. For system specification we have used the UML state chart diagram, from which event tree is generated. Along with a case study an algorithm is proposed to generate the test suite and confirm whether it is free from deadlock.

关键词： Concurrency state chart diagram Deadlock Event Tree Test Sequences

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Development of plant DiD Risk Monitor system for NPPs by utilizing UML modelling technology

Development of plant DiD Risk Monitor system for NPPs by uti...

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13th IFAC/IFIP/IFORS/IEA Symposium on Analysis, Design, and Evaluation of Human-Machine Systems (HMS)

作者： Yoshikawa, Hidekazu Nakagawa, Takashi Symbio Community Forum Kyoto Japan Prime Syst Lab Co Ltd Kawanishi Japan

A new risk monitor system is under development which can be applied not only to prevent severe accident in daily operation but also to serve as to mitigate the radiological hazard just after severe accident happens. The system simulates these applied situations, by generating interactions among all actors such as the plant and related people coping with the accident. In this paper, the plant DiD risk monitor is developed utilizing Unified Modeling Language (UML) to model actors' knowledge and express the interactions. Case study to confirm functionality and ability of DiD risk monitor is also introduced by showing examples for Station blackout accident in conventional PWR plant in Japan. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： defense-in depth risk monitor system object oriented program unified modeling language state chart diagram sequence diagram

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Test Case Generation and Optimization using UML Models and Genetic Algorithm 3

Test Case Generation and Optimization using UML Models and G...

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3rd International Conference on Recent Trends in Computing (ICRTC)

作者： Khurana, Namita Chillar, R. S. MDU Dept Comp Sci & Applicat Rohtak 124001 Haryana India

Software testing plays an important role in software development because it can minimize the development cost. Software testing approaches are divided into three parts i.e. code based testing, specification based testing and model based testing. In model based testing, the testing begins at design phase. So, early detection of faults can be achieved by using this approach further reducing time, cost and efforts of the developer to a large extent. In this paper we propose a technique for generating test cases using both UML sequence diagram and state chart diagram. Our approach is to convert Sequence diagram into Sequence Graph and then to convert state chart diagram into state chart Graph. Finally System Testing Graph (SYTG) is formed by combining the two Graphs. From the graphs different control flow sequences also called test cases are identified and then optimized using evolutionary Algorithm, called Genetic Algorithm. Although state chart did better at revealing unit level faults and sequence diagram is better at removing integration level faults, but after integrating the two graphs, generated test cases are appropriate for system testing and to identify Error handling, correctness, pre-post condition faults, interaction, message sequence faults and scenario faults. (C) 2015 Published by Elsevier B.V.

关键词： Sequence diagram state chart diagram System Testing Graph Online Voting system Genetic Algorithm

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Test Case Generation and Optimization using UML Models and Genetic Algorithm

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Procedia Computer Science 2015年 57卷 996-1004页

作者： Namita Khurana R.S. Chillar Deptt. Of Comp. Sc. and Applications M.D.U Rohtak-124001 India

关键词： Sequence diagram state chart diagram System Testing Graph Online Voting system Genetic Algorithm

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Consistency checking between two different dynamic views of a software system

Consistency checking between two different dynamic views of ...

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10th IASTED International Conference on Software Engineering and Applications

作者： Shen, Wuwei Low, Weng Liong Western Michigan Univ Dept Comp Sci Kalamazoo MI 49008 USA Microsoft Corp Redmond WA 98052 USA

ISBN: (纸本)9780889866423

Complexity is the distinguishing characteristic of modem software. A software model designed by the Unified Modeling Language often consists of a set of UML diagrams. Particularly, the dynamic aspect of a software system can be modelled by state chart diagrams and sequence diagrams. But, inconsistencies between these two diagrams such as different message orders hinder the understanding of the dynamic behavior of a model, thus possibly causing a final system to failure. In this paper, we propose to build a message graph from a state chart diagram and then go through the graph based on the sequence of the messages retrieved from a sequence diagram to find any inconsistency between these two diagrams. Based on this method, a tool called ICER is developed to provide software developers with automatic consistency checking in the dynamic aspects of a model.

关键词： state chart diagram sequence diagram message passing UML

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