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string-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

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MICROELECTRONICS JOURNAL 2024年 153卷

作者： Cho, Sunghwan Choi, Byoungdeog Sungkyunkwan Univ Dept Semicond & Display Engn Suwon 16419 South Korea Samsung Elect Co Memory Business Hwasung 18448 South Korea Sungkyunkwan Univ Dept Elect & Comp Engn Suwon 16419 South Korea

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

关键词： 3D charge trapping flash (CTF) memory string-level compact model Erase operation Framework Circuit simulation

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