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Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator

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JOURNAL OF SYSTEMS ARCHITECTURE 2019年 98卷 173-190页

作者： Fu, Sheng-Yu Hong, Ding-Yong Liu, Yu-Ping Wu, Jan-Jan Hsu, Wei-Chung Natl Taiwan Univ Comp Sci Taipei Taiwan Natl Taiwan Univ Taipei Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Acad Sinica Inst Informat Sci Taipei Taiwan Acad Sinica Inst Informat Sci Comp Syst Lab Taipei Taiwan

More and more modern processors have been supporting non-contiguous SIMD data accesses. However, translating such instructions has been overlooked in the Dynamic Binary Translation (DBT) area. For example, in the popular QEMU dynamic binary translator, guest memory instructions with strides are emulated by a sequence of scalar instructions, leaving a significant room for performance improvement when the SIMD instructions are available on the host machines. structured loads/stores, such as VLDn/VSTn in ARM NEON, are one type of strided SIMD data access instructions. They are widely used in signal processing, multimedia, mathematical, and 2D matrix transposition applications. Efficient translation of such structured loads/stores is a critical issue when migrating ARM executables to other ISAs. However, it is quite challenging since not only the translation of structured loads/stores is not trivial, but also the mapping of SIMD registers between guest and host is complicated. This paper presents the design of translating structured loads/stores in DBT, including target code generation, efficient SIMD register mapping, and optimizations for reducing data permutations. Our proposed register mapping mechanisms and optimizations are not limited to handle structured loads/stores, they can be extended to deal with normal SIMD instructions. This paper evaluates how different factors affect the translation performance and code size. These factors include guest SIMD register length, strides, and use cases for structured loads. On a set of OpenCV benchmarks, our QEMU-based system has achieved a maximum speedup of 5.03x, with an average improvement of 2.87x. On a set of BLAS benchmarks, our system has obtained a maximum speedup of 2.22x and an average improvement of 1.78x.

关键词： SIMD Dynamic binary translation structured load/store SIMD register mapping

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Dynamic Translation of structured loads/stores and Register Mapping for Architectures with SIMD Extensions 2017

Dynamic Translation of Structured Loads/Stores and Register ...

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18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES)

作者： Fu, Sheng-Yu Hong, Ding-Yong Liu, Yu-Ping Wu, Jan-Jan Hsu, Wei-Chung Natl Taiwan Univ Taipei Taiwan Acad Sinica Taipei Taiwan

ISBN: (纸本)9781450350303

More and more modern processors have been supporting non-contiguous SIMD data accesses. However, translating such instructions has been overlooked in the Dynamic Binary Translation (DBT) area. For example, in the popular QEMU dynamic binary translator, guest memory instructions with strides are emulated by a sequence of scalar instructions, leaving a significant room for performance improvement when the host machines have SIMD instructions available. structured loads/stores, such as VLDn/VSTn in ARM NEON, are one type of strided SIMD data access instructions. They are widely used in signal processing, multimedia, mathematical and 2D matrix transposition applications. Efficient translation of such structured loads/stores is a critical issue when migrating ARM executables to other ISAs. However, it is quite challenging since not only the translation of structured loads/stores is not trivial, but also the difference between guest and host register configurations must be taken into consideration. In this work, we present the design and implementation of translating structured loads/stores in DBT, including target code generation as well as efficient SIMD register mapping. Our proposed register mapping mechanisms are not limited to handling structured loads/stores, they can be extended to deal with normal SIMD instructions. On a set of OpenCV benchmarks, our QEMU-based system has achieved a maximum speedup of 5.41x, with an average improvement of 2.93x. On a set of BLAS benchmarks, our system has also obtained a maximum speedup of 2.19x and an average improvement of 1.63x.

关键词： SIMD Dynamic Binary Translation structured load/store Register Mapping

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