We present an algorithm for finding the maximum dow in a 0-1 network. The algorithm is symbolic and does not require explicit enumeration of the nodes and edges of the network. Therefore, it can handle much larger gra...
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We present an algorithm for finding the maximum dow in a 0-1 network. The algorithm is symbolic and does not require explicit enumeration of the nodes and edges of the network. Therefore, it can handle much larger graphs than it was previously possible (more than 10(36) edges). The main idea is to trace (implicitly) sets of edge-disjoint augmenting paths. Disjointness is enforced by solving an edge matching problem for each layer of the network with the help of newly defined priority functions.
This paper presents applications of algebraic decision diagrams (ADD's) to timing analysis and resynthesis for low power of combinational CMOS circuits, We first propose a symbolic algorithm to perform true delay ...
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This paper presents applications of algebraic decision diagrams (ADD's) to timing analysis and resynthesis for low power of combinational CMOS circuits, We first propose a symbolic algorithm to perform true delay calculation of a technology mapped network;the procedure we propose, implemented as an extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far;in particular, it is able to compute and store the arrival times of all the gates of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst case primary inputs combination, Furthermore, the approach does not require any explicit false path elimination, We then extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to perform resynthesis for low power of the circuit by gate resizing, Our approach takes into account false paths naturally;in fact, it guarantees that resizing of the gates does not increase the true delay of the circuit, even in the presence of false paths, Our experiments have shown that many circuits, originally free of false paths, exhibit a large number of these false paths when optimized for area;therefore, the ability to deal with circuits containing false paths is of primary importance, We present experimental results for ADD-based and static timing analysis-based resynthesis, which clearly show that our tool is superior in the case of circuits containing false paths, but at the same time, it provides competitive results in the case of circuits which are free of false paths.
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