Ultra-wideband (UWB) wireless communication systems are based on the transmission of extremely narrow pulses, with a duration inferior to a nanosecond. The application of transmit reference (TR) to UWB systems allows ...
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Ultra-wideband (UWB) wireless communication systems are based on the transmission of extremely narrow pulses, with a duration inferior to a nanosecond. The application of transmit reference (TR) to UWB systems allows to side-step channel estimation at the receiver, with a tradeoff the effective transmission bandwidth, which is reduced by the usage of a reference pulse. Similar to CDMA systems, different users can share the same available bandwidth by means of different spreading codes. This allows the receiver to separate users, and to recover the timing information of the transmitted data packets. The nature of UWB transmissions-short, burst-like packets-requires a fast synchronization algorithm, that can accommodate several asynchronous users. Exploiting the fact that a shift in time corresponds to a phase rotation in the frequency domain, a blind and computationally efficient synchronization algorithm that takes advantage of the shift invariance structure in the frequency domain is proposed in this paper. Integer and fractional delay estimations are considered, along with a subsequent symbol estimation step. This results in a collision-avoiding multiuser algorithm, readily applicable to a fast acquisition procedure in a UWB ad hoc network. Copyright (C) 2006 Relja Djapic et al.
VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorith...
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VHDL-AMS is the Analog and Mixed-Signal Extensions to VHDL. The paper gives a brief overview of the added features to VHDL. A mixed-signal simulator has been developed based on VHDL-AMS. A new synchronization algorithm is adopted in the simulator. Using the new algorithm the analog kernel does not need to synchronize the digital kernel at each digital event time point. The efficiency of the new synchronization algorithm is tested by examples. Simulation results show the newly developed algorithm can speed up the simulation.
Time synchronization is the key foundation of all applications of distributed *** are two kinds of implement method on time synchronization:the absolute time synchronization and relative lime synchronization,the forme...
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Time synchronization is the key foundation of all applications of distributed *** are two kinds of implement method on time synchronization:the absolute time synchronization and relative lime synchronization,the former needs an external time to be as a Primary Reference Source (PRS),the latter can be realized only by executing synchronization algorithm inside the distributed *** this paper,some lime synchronization algorithms used in LAN were discussed in detail,and some application results with some algorithm were also analyzed.
The variation of packet-arrival intervals is one of the problems to be solved in realizing real-time voice communications on asynchronous networks such as the Internet. Although the variation can be absorbed by a rece...
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Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution t...
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Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution time required by simulation is becoming more and more significant. Faster logic simulators will have an appreciable economic impact, speeding time to market while ensuring more thorough system design testing. One approach to this problem is to utilize parallel processing, taking advantage of the concurrency available in the VLSI system to accelerate the logic simulation task. Parallel logic simulation has received a great deal of attention over the past several years, but this work has not yet resulted in effective, high-performance simulators being available to VLSI designers. A number of techniques have been developed to investigate performance issues: formal models, performance modeling, empirical studies, and prototype implementations. Analyzing reported results of these techniques, we conclude that five major factors effect performance: synchronization algorithm, circuit structure, timing granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the results and present directions for future research in the field.
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