We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method o...
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We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform. but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP bur also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.
Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most...
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ISBN:
(纸本)9780769543833
Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most important reasons for that, is the lack of asynchronous Electronic Design Automation (EDA) tools and the fact that existing EDA tools are not suitable for asynchronous implementations. Moreover, physical EDA tools, like placement algorithms, involve methodologies which are not applicable to asynchronous circuits, such as static timing analysis (STA) which cannot be performed in a cyclic circuit. In this work, we present CPlace, a constructive placement algorithm which can efficiently handle asynchronous circuits. We use timing separation of events for timing analysis and maintain the quasi-delay insensitive (QDI) properties by bounding the relative delays of wires in isochronic forks. We employ absolute timing constraints for performance and relative timing constraints for QDI which are handled by an ILP formulation. Experimental results show the effectiveness of CPlace in respecting QDI constraints against a synchronous, state-of-the-art industrial placer and a well-known academic placer.
The use of deeper-submicron technologies in integrated circuits worsens the effects of transient faults. In fact, the transient-fault durations become as important as the clock periods of synchronous circuits. Electro...
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The use of deeper-submicron technologies in integrated circuits worsens the effects of transient faults. In fact, the transient-fault durations become as important as the clock periods of synchronous circuits. Electronic systems are thus more vulnerable to failure situations. Nevertheless, this paper shows innovatively that such a worse scenario does not happen in asynchronous circuits. This additional novel benefit pushes on the asynchronous design as a better alternative to mitigate transient faults in deep-submicron technology-based circuits. (C) 2010 Elsevier Ltd. All rights reserved.
The paper presents the system analysis and circuit design of a half-bridge zero-voltage-switching (ZVS) flyback converter with synchronous rectifier. The leakage inductance and output capacitance of active switches ar...
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The paper presents the system analysis and circuit design of a half-bridge zero-voltage-switching (ZVS) flyback converter with synchronous rectifier. The leakage inductance and output capacitance of active switches are used to realise ZVS operation during the transition state between two switches. The switching power loss of active switches can be reduced to a minimum due to the ZVS operation such that the high-efficiency circuit can be achieved. The circuit-operation principle, mathematical analysis and design example of a half-bridge ZVS flyback converter with synchronous rectifier are explained and analysed. The synchronous rectifier is used at the transformer-secondary side to reduce further the conduction loss and to increase the circuit efficiency. Finally the experimental results from a 24V/7A output load with 100kHz switching-frequency prototype circuit are provided to verify the theoretical analysis.
In this paper, we introduce a reconfigurable oscillatory network that generates a synchronous and distributed clocking signal. We propose an accurate model of the network to facilitate the study of its design space an...
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In this paper, we introduce a reconfigurable oscillatory network that generates a synchronous and distributed clocking signal. We propose an accurate model of the network to facilitate the study of its design space and ensure that it operates in its optimal, synchronous mode. The network is designed and implemented in a fully integrated 65-nm CMOS system-on-chip that utilizes coupled all digital phase locked loops interconnected as a Cartesian grid. The model and measurements demonstrate frequency and phase synchronization even in the presence of noise and random initial conditions. This network is proposed for small-scale multiple input multiple-output systems that require complete synchronization both in frequency and in phase.
Time domain synchronous OFDM outperforms cyclic prefix OFDM in spectral efficiency and fast synchronisation, but suffers from the difficulty of supporting 256QAM and the performance loss over doubly selective fading c...
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Time domain synchronous OFDM outperforms cyclic prefix OFDM in spectral efficiency and fast synchronisation, but suffers from the difficulty of supporting 256QAM and the performance loss over doubly selective fading channels due to severe inter-block-interference (IBI). In this reported work, the groundbreaking theory of compressive sensing is explored to solve those open problems, whereby the IBI-free region of small size within the received training sequence is used to recover the high-dimensional channel without any IBI cancellation, and partial priori information of the channel is further exploited to reduce the complexity.
synchronous combinational complexity, a measure of the size of logic circuits without races, is investigated in this paper. The first author has presented a method for obtaining an O(nlogn)<math xmlns="http://...
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synchronous combinational complexity, a measure of the size of logic circuits without races, is investigated in this paper. The first author has presented a method for obtaining an O(nlogn)
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