检索结果-内蒙古大学图书馆

Estimating Latency for synchronous dataflow Graphs Using Periodic Schedules 1

13th International Conference on Verification and Evaluation of Computer and Communication Systems (VECoS)

作者： Glanon, Philippe Azaiez, Selma Mraidha, Chokri CEA LIST Saclay Gif Sur Yvette France

ISBN: (数字)9783030350925

ISBN: (纸本)9783030350925;9783030350918

synchronous dataflow Graph (SDFG) is a formal tool widely used to model and analyze the behaviour of systems constrained by timing requirements. It has been successfully used in digital signal processing and manufacturing fields to specify and analyze the performance of embedded and distributed applications. Various performance indicators such as throughput, latency or memory consumption can be evaluated with SDFGs. This paper tackles the latency analysis for SDFG using periodic schedules.

关键词： synchronous dataflow Latency Periodic schedules

来源：评论

学校读者我要写书评

暂无评论

Scheduling of Parallelized synchronous dataflow Actors for Multicore Signal Processing

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第3期83卷 309-328页

作者： Zhou, Zheng Plishker, William Bhattacharyya, Shuvra S. Desnos, Karol Pelcat, Maxime Nezan, Jean-Francois Texas Instruments Inc Germantown MD USA Univ Maryland Dept ECE & UMIACS College Pk MD 20742 USA UEB CNRS INSA Rennes IETRUMR 6164 Rennes France

Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as synchronous dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra-and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) - PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a soft

关键词： Multicore processors Digital signal processors synchronous dataflow dataflow modeling Software synthesis

来源：评论

学校读者我要写书评

暂无评论

RDF: A Reconfigurable dataflow Model of Computation

引用

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2023年第1期22卷 1-30页

作者： Fradet, Pascal Girault, Alain Krishnaswamy, Ruby Nicollin, Xavier Shafiei, Arash Univ Grenoble Alpes INRIA CNRS Grenoble INPLIG Orange France Orange Labs 140 Ave Republ F-92320 Chatillon France

dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the first and most popular dataflow MoCs, synchronous dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lack the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment. We address this need by proposing a new MoC called Reconfigurable dataflow (RDF). RDF extends SDF with transformation rules that specify how and when the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and present its implementation and some experimental results.

关键词： Models of computation synchronous dataflow reconfigurable systems graph rewriting static analyses boundedness liveness

来源：评论

学校读者我要写书评

暂无评论

dataflow Model-based Software Synthesis Framework for Parallel and Distributed Embedded Systems

引用

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2021年第5期26卷 1–38页

作者： Jeong, Eunjin Jeong, Dowhan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Seoul South Korea

Existing software development methodologies mostly assume that an application runs on a single device without concern about the non-functional requirements of an embedded system such as latency and resource consumption. Besides, embedded software is usually developed after the hardware platform is determined, since a non-negligible portion of the code depends on the hardware platform. In this article, we present a novel model-based software synthesis framework for parallel and distributed embedded systems. An application is specified as a set of tasks with the given rules for execution and communication. Having such rules enables us to perform static analysis to check some software errors at compile-time to reduce the verification difficulty. Platform-specific programs are synthesized automatically after the mapping of tasks onto processing elements is determined. The proposed framework is expandable to support new hardware platforms easily. The proposed communication code synthesis method is extensible and flexible to support various communication methods between devices. In addition, the fault-tolerant feature can be added by modifying the task graph automatically according to the selected fault-tolerance configurations by the user. The viability of the proposed software development methodology is evaluated with a real-life surveillance application that runs on six processing elements.

关键词： Code generation fault tolerance synchronous dataflow embedded soft-ware development

来源：评论

学校读者我要写书评

暂无评论

Analysis and Identification of Possible Automation Approaches for Embedded Systems Design Flows

引用

INFORMATION 2020年第2期11卷 120-120页

作者： Horita, Augusto Y. Loubach, Denis S. Bonna, Ricardo Univ Estadual Campinas Adv Comp Control & Embedded Syst Lab FEM UNICAMP BR-13083860 Campinas SP Brazil Aeronaut Inst Technol ITA Dept Comp Syst Comp Sci Div BR-12228900 Sao Jose Dos Campos SP Brazil

Sophisticated and high performance embedded systems are present in an increasing number of application domains. In this context, formal-based design methods have been studied to make the development process robust and scalable. Models of computation (MoC) allows the modeling of an application at a high abstraction level by using a formal base. This enables analysis before the application moves to the implementation phase. Different tools and frameworks supporting MoCs have been developed. Some of them can simulate the models and also verify their functionality and feasibility before the next design steps. In view of this, we present a novel method for analysis and identification of possible automation approaches applicable to embedded systems design flow supported by formal models of computation. A comprehensive case study shows the potential and applicability of our method.

关键词： modeling simulation formal models of computation synchronous synchronous dataflow scenario-aware dataflow

来源：评论

学校读者我要写书评

暂无评论

TIME-PREDICTABLE SOFTWARE-DEFINED ARCHITECTURE WITH SDF-BASED COMPILER FLOWFOR 5G BASEBAND PROCESSING

TIME-PREDICTABLE SOFTWARE-DEFINED ARCHITECTURE WITH SDF-BASE...

引用

IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Venkataramani, Vanchinathan Bodin, Bruno Kulkarni, Aditi Mitra, Tulika Peh, Li-Shivan Natl Univ Singapore Sch Comp Singapore Singapore Natl Univ Singapore Yale NUS Coll Singapore Singapore

ISBN: (纸本)9781509066315

The advent of 5G networks motivates the need for highperformance, low-power, time-predictable hardware that can handle the aggressive real-time latency and throughput requirements of baseband processing. With newer generations like 5G, programmable hardware that can adapt readily to network specification updates becomes a critical requirement. We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing guarantees with a programmable architecture. Our architecture and compiler flow are designed to support basestation baseband processing computation represented using deterministic synchronous Data Flow (SDF) model of computation. SDF is commonly used to represent signal processing applications and fits well with real-time systems requirements. We demonstrate substantial power savings with SPECTRUM compared to existing DSPs while meeting the performance requirements.

关键词： Time-predictability many-core architecture LTE/5G baseband processing synchronous dataflow

来源：评论

学校读者我要写书评

暂无评论

Latency Evaluation of SDFGs on Heterogeneous Processors Using Timed Automata

引用

IEEE ACCESS 2020年 8卷 140171-140180页

作者： Rajadurai, Sivashankari Alazab, Mamoun Kumar, Neeraj Gadekallu, Thippa Reddy Vellore Inst Technol Sch Informat Technol & Engn Vellore 632014 Tamil Nadu India Charles Darwin Univ Coll Engn IT & Environm Casuarina NT 0909 Australia Thapar Inst Engn & Technol Dept Comp Sci & Engn Patiala 147001 Punjab India Asia Univ Dept Comp Sci & Informat Engn Taichung 41354 Taiwan

synchronous Data Flow (SDF) is a graphical computation model used for analyzing digital signal processing and real time multimedia applications. In general, these applications have two primary performance metrics - throughput and latency. Latency is important in multimedia processing applications such as video-conferencing, Internet telephony and games since latency surpassing a specific limit results in poor quality of service (QoS). Past work had focused on computing the latency of SDF graphs on homogeneous multiprocessor platforms. In this paper, we present an approach to compute the latency of a static schedule for a given unfolding factor with an optimal throughput for an SDF graph on a heterogeneous multiprocessor platform using timed automata. We use timed automata as a semantic model to represent the system model, which includes a synchronous data flow graph and an execution platform. We use the UPPAAL model-checker to specify the resulting network of timed automata and compute the latency.

关键词： Throughput Schedules Automata Program processors Computational modeling Data models Real-time systems synchronous dataflow throughput latency timed automata UPPAAL

来源：评论

学校读者我要写书评

暂无评论

RDF: Reconfigurable dataflow 22

RDF: Reconfigurable Dataflow

引用

22nd Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Fradet, Pascal Girault, Alain Krishnaswamy, Ruby Nicollin, Xavier Shafiei, Arash Univ Grenoble Alpes INRIA CNRS Grenoble INPLIG F-38000 Grenoble France Orange Paris France

ISBN: (纸本)9783981926323

dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the most popular dataflow MoCs, synchronous dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF (and most of its variants) lacks the capability to express the dynamism needed by modern streaming applications. In particular, the applications mentioned above have a strong need for reconfigurability to accommodate changes in the input data, the control objectives, or the environment. We address this need by proposing a new MoC called Reconfigurable dataflow (RDF). RDF extends SDF with transformation rules that specify how the topology and actors of the graph may be reconfigured. Starting from an initial RDF graph and a set of transformation rules, an arbitrary number of new RDF graphs can be generated at runtime. A key feature of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be consistent and live. We introduce the RDF MoC, describe its associated static analyses, and outline its implementation.

关键词： Models of computation synchronous dataflow Reconfigurable systems Static analyses Boundedness Liveness

来源：评论

学校读者我要写书评

暂无评论

Executing synchronous dataflow Graphs on a SPM-Based Multicore Architecture 12

Executing Synchronous Dataflow Graphs on a SPM-Based Multico...

引用

49th ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Choi, Junchul Oh, Hyunok Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea Hanyang Univ Dept Informat Syst Seoul South Korea Chonbuk Natl Univ Dept Comp Sci & Engn Jeonju South Korea

ISBN: (纸本)9781450311991

In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a non-optimized approach and the previous approach.

关键词： Multiprocessor scheduling synchronous dataflow scratch pad memory multicore architecture memory overlay prefetching

来源：评论

学校读者我要写书评

暂无评论

Development of a real-time non-intrusive appliance load monitoring system: An application level model

引用

INTERNATIONAL JOURNAL OF ELECTRICAL POWER & ENERGY SYSTEMS 2017年 90卷 168-180页

作者： Trung Kien Nguyen Dekneuvel, Eric Jacquemod, Gilles Nicolle, Benjamin Zammit, Olivier Van Cuong Nguyen Univ Sci & Technol Da Nang Vietnam Univ Nice Sophia Antipolis EPOC UNS Sophia Antipolis France Qualisteo Co Nice France

The research "Behavior Change and Energy Use" (US Department of Energy and Climate Change, 2011) [1] shows that with better information in the monthly electricity bill, the Energy Performance Certificate (EPC) can encourage people to reduce their energy usage. That is why smart meters - the emerging technology to help people to know their monthly energy consumption, are gradually replacing mechanical power meters. In this paper, we investigate a special energy monitoring process named Non-Intrusive Appliance Load Monitoring (NIALM), which is potentially the best method to give consumers pertinent information with respect to power consumption. However, real-time feedback feature in a low cost NIALM system is still a big challenge in such technology because of the complication in NIALM's algorithms. System on Chip (SoC) technology can solve this challenge. Besides including high-speed interconnection and multi-processors, integrating Field-Programmable Gate Array (FPGA) into SoCs may be the most important evolution, which provides developers a powerful tool to develop a low cost but high performance system. Therefore, in this paper we proposed a development of a real-time NIALM system based on the SoC with FPGA acceleration. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： NIALM CUSUM Genetic algorithm K-mean FPGA System modeling Hardware software co-development synchronous dataflow

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：