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9th International Multitopic Conference of Pakistan

作者： Khan, Ahmad Khalil Jamal, Habibullah Univ Engn & Technol Fac Elect Engn Taxila Pakistan

ISBN: (纸本)9780780394292

This paper presents an architectural framework of a motion detection and compression system for surveillance applications. The emphasis is on use of a dataflow based design paradigm that can be dynamically linked to an extensible framework for simulation and algorithm development. The framework is based on Ptolemy II software environment and is built around synchronous dataflow (SDF) domain. It employs Ptolemy's flexibility for the development of functional and behavioral simulations and rapid protyping of embedded systems.

关键词： synchronous dataflow video processing motion detection phototyping modeling and simulation

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Scheduling of Parallelized synchronous dataflow Actors for Multicore Signal Processing

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2016年第3期83卷 309-328页

作者： Zhou, Zheng Plishker, William Bhattacharyya, Shuvra S. Desnos, Karol Pelcat, Maxime Nezan, Jean-Francois Texas Instruments Inc Germantown MD USA Univ Maryland Dept ECE & UMIACS College Pk MD 20742 USA UEB CNRS INSA Rennes IETRUMR 6164 Rennes France

Parallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as synchronous dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra-and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) - PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a soft

关键词： Multicore processors Digital signal processors synchronous dataflow dataflow modeling Software synthesis

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Multithreaded Simulation for synchronous dataflow Graphs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2011年第3期16卷 1–23页

作者： Hsu, Chia-Jui Pino, Jose Luis Bhattacharyya, Shuvra S. Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

For system simulation, synchronous dataflow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and execute static schedules in single-processor desktop environments. Nowadays, however, multicore processors are increasingly popular desktop platforms for their potential performance improvements through thread-level parallelism. Without novel scheduling and simulation techniques that explicitly explore thread-level parallelism for executing SDF graphs, current design tools gain only minimal performance improvements on multicore platforms. In this article, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speedup for executing SDF graphs on multicore processors. MSS strategically integrates graph clustering, intracluster scheduling, actor vectorization, and intercluster buffering techniques to construct InterThread Communication (ITC) graphs at compile-time. MSS then applies efficient synchronization and dynamic scheduling techniques at runtime for executing ITC graphs in multithreaded environments. We have implemented MSS in the Advanced Design System (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speedup in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).

关键词： Algorithms Design synchronous dataflow multithreaded simulation scheduling

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Extended synchronous dataflow for efficient DSP system prototyping

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2002年第3期6卷 295-322页

作者： Park, C Jung, J Ha, S Seoul Natl Univ Sch Engn & Comp Sci Seoul South Korea Thinkware Syst Corp Seoul South Korea

Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes it unsuitable for multimedia signal processing applications that need global states for efficient implementation. In this paper, we propose synchronous piggybacked dataflow (SPDF), an extension of SDF model to accommodate global states without side effects. Global states are accessed by a special block that piggybacks the global state update request on data samples. Such an extension enlarges the domain of application where dataflow representation can be used for rapid system prototyping. The only penalty it incurs is scheduling complexity since the scheduler now considers control dependency as well as data dependency. We present the static analysis of the SPDF model and an implementation technique for memory efficient code synthesis. Finally, we show experimental results with a real life example, MPEG-audio decoder, to present the novelty and usefulness of our approach.

关键词： synchronous dataflow global states synchronous piggybacked dataflow block reusability

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Throughput-buffering trade-off exploration for cyclo-static and synchronous dataflow graphs

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IEEE TRANSACTIONS ON COMPUTERS 2008年第10期57卷 1331-1345页

作者： Stuijk, Sander Geilen, Marc Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5612 AB Eindhoven Netherlands

Multimedia applications usually have throughput constraints. An implementation must meet these constraints while it minimizes resource usage and energy consumption. The compute intensive kernels of these applications are often specified as Cyclo-Static or synchronous dataflow Graphs. Communication between nodes in these graphs requires storage space, which influences throughput. We present an exact technique to chart the Pareto space of throughput and storage trade-offs, which can be used to determine the minimal buffer space needed to execute a graph under a given throughput constraint. The feasibility of the exact technique is demonstrated with experiments on a set of realistic DSP and multimedia applications. To increase the scalability of the approach, a fast approximation technique is developed that guarantees both throughput and a tight bound on the maximal overestimation of buffer requirements. The approximation technique allows us to trade off worst-case overestimation versus runtime.

关键词： cyclo-static dataflow synchronous dataflow buffering throughput optimization Pareto analysis trade-offs DSP multimedia applications

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Joint minimization of code and data for synchronous dataflow programs

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FORMAL METHODS IN SYSTEM DESIGN 1997年第1期11卷 41-70页

作者： Murthy, PK Bhattacharyya, SS Lee, EA UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720 HITACHI AMER LTD SEMICOND RES LABSAN JOSECA 95134

In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [21], which has been used heavily in DSP design environments over the past several years. We first focus on the restricted class of well-ordered SDF graphs. We show that while extremely efficient techniques exist for constructing minimum code size schedules for well-ordered graphs, the number of distinct minimum code size schedules increases combinatorially with the number of vertices in the input SDF graph, and these different schedules can have vastly different data memory requirements. We develop a dynamic programming algorithm that computes the schedule that minimizes the data memory requirement from among the schedules that minimize code size, and we show that the time complexity of this algorithm is cubic in the number of vertices in the given well-ordered SDF graph. We present several extensions to this dynamic programming technique to more general scheduling problems, and we present a heuristic that often computes near-optimal schedules with quadratic time complexity. We then show that finding optimal solutions for arbitrary acyclic graphs is NP-complete, and present heuristic techniques that jointly minimize code and data size requirements. We present a practical example and simulation data that demonstrate the effectiveness of these techniques.

关键词： dataflow programming synchronous dataflow memory management multirate signal processing algorithms SDF compiler on-chip memory minimum cuts dynamic programming

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Buffer merging - A powerful technique for reducing memory requirements of synchronous dataflow specifications

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2004年第2期9卷 212-237页

作者： Murthy, PK Bhattacharyya, SS Fujitsu Labs Amer Sunnyvale CA 94085 USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Univ Maryland Inst Adv Comp Studies College Pk MD 20742 USA

We develop a new technique called buffer merging for reducing memory requirements of synchronous dataflow (SDF) specifications. SDF has proven to be an attractive model for specifying DSP systems, and is used in many commercial tools like System Canvas, SPW, and Cocentric. Good synthesis from an SDF specification depends crucially on scheduling, and memory is an important metric for generating efficient schedules. Previous techniques on memory minimization have either not considered buffer sharing at all, or have done so at a fairly coarse level (the meaning of this will be made more precise in the article). In this article, we develop a buffer overlaying strategy that works at the level of an input/output edge pair of an actor. It works by algebraically encapsulating the lifetimes of the tokens on the input/output edge pair, and determines the maximum amount of the input buffer space that can be reused by the output. We develop the mathematical basis for performing merging operations, and develop several algorithms and heuristics for using the merging technique for generating efficient implementations. We show improvements of up to 48% over previous techniques.

关键词： algorithms design languages synchronous dataflow memory optimization lifetime analysis graph coloring buffer overlaying path covering array lifetime design methodology DSP and embedded systems block diagram compiler dataflow

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Efficient Software Synthesis for Dynamic Single Appearance Scheduling of synchronous dataflow

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IEEE EMBEDDED SYSTEMS LETTERS 2009年第3期1卷 69-72页

作者： Liu, Weichen Gu, Zonghua Xu, Jiang Hong Kong Univ Sci & Technol Hong Kong Hong Kong Peoples R China Zhejiang Univ Hangzhou Peoples R China

synchronous dataflow (SDF) is a widely-used model of computation for digital signal processing and multimedia applications. In this letter, we propose an automatic approach to synthesize efficient software from SDF models with improved runtime efficiency. Our synthesis technique is based on dynamic single-appearance scheduling (dynSAS), which generates software with minimized code size, the same as traditional single-appearance schedule (SAS), while requires much less buffer memory space. We enhance dynSAS systematically to reduce control flow overhead and increase memory utilization. Experiment results show that our approach can generate efficient software with enhanced runtime performance compared to related techniques.

关键词： Genetic algorithms scheduling software synthesis synchronous dataflow

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Efficient simulation of critical synchronous dataflow graphs

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2007年第3期12卷 1–28页

作者： Hsu, Chia-Jui Ko, Ming-Yung Bhattacharyya, Shuvra S. Ramasubbu, Suren Pino, Jose Luis Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Agilent Technol Palo Alto CA 94306 USA

System-level modeling, simulation, and synthesis using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems, and the synchronous dataflow (SDF) model of computation is widely used in EDA tools for these purposes. Behavioral representations of modern wireless communication systems typically result in critical SDF graphs: These consist of hundreds of components (or more) and involve complex intercomponent connections with highly multirate relationships (i.e., with large variations in average rates of data transfer or component execution across different subsystems). Simulating such systems using conventional SDF scheduling techniques generally leads to unacceptable simulation time and memory requirements on modern workstations and high-end PCs. In this article, we present a novel simulation-oriented scheduler (SOS) that strategically integrates several techniques for graph decomposition and SDF scheduling to provide effective, joint minimization of time and memory requirements for simulating critical SDF graphs. We have implemented SOS in the advanced design system (ADS) from Agilent Technologies. Our results from this implementation demonstrate large improvements in simulating real-world, large-scale, and highly multirate wireless communication systems (e.g., 3GPP, Bluetooth, 802.16e, CDMA 2000, XM radio, EDGE, and Digital TV).

关键词： algorithms design scheduling simulation synchronous dataflow

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Multithreaded simulation for synchronous dataflow graphs

Multithreaded simulation for synchronous dataflow graphs

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45th ACM/IEEE Design Automation Conference

作者： Hsu, Chia-Jui Pino, Jose Luis Bhattacharyya, Shuvra S. Agilent Technol Westlake Village CA 91362 USA Univ Maryland Dept ECE Dept UMIACS College Pk MD 20742 USA

ISBN: (纸本)9781605581156

synchronous dataflow (SDF) has been successfully used in design tools for system-level simulation of wireless communication systems. Modern wireless communication standards involve large complexity and highly-multirate behavior, and typically result in long simulation time. The traditional approach for simulating SDF graphs is to compute and execute static single-processor schedules. Nowadays, multi-core processors are increasingly popular for their potential performance improvements through on-chip, thread-level paxallelism. However, without novel scheduling and simulation techniques that explicitly explore multithreading capability, current design tools gain only minimal performance improvements. In this paper, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speed-up for executing SDF graphs on multi-core processors. We have implemented MSS in the Advanced Design System (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speed-up in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).

关键词： synchronous dataflow multithreaded simulation scheduling

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