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synthesis of clock tree topologies to implement nonzero clock skew schedule

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1999年第6期146卷 321-326页

作者： Kourtev, IS Friedman, EG Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

Designing the topology of a clock distribution network is considered for a synchronous digital integrated circuit so as to satisfy a nonzero clock skew schedule. A methodology and related algorithms for synthesising the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming problem. The approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to 64% performance improvement is attained on these circuits by exploiting nonzero clock skew throughout the synchronous system. Clock tree topologies that implement the nonzero clock skew schedule based on the synthesis algorithms presented are described for each of the benchmark circuits.

关键词： clocks clock distribution network synthesis algorithms VLSI circuit timing information ISCAS'89 benchmark circuits integer programming integer linear programming problem nonzero clock skew schedule synchronous digital integrated circuit timing integrated circuit design linear programming logic CAD clock tree topologies

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Fast phase-only synthesis of conformal reflectarrays

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IET MICROWAVES ANTENNAS & PROPAGATION 2010年第12期4卷 1989-2000页

作者： Capozzoli, A. Curcio, C. D'Elia, G. Liseno, A. Univ Naples Federico II DIBET I-80125 Naples Italy

Phase-only synthesis (POS) techniques represent an important tool for reflectarray design. Indeed, although based on approximate scattering models, for planar antennas, they are numerically effective thanks to the use of fast Fourier transform (FFT) routines. Conformal reflectarrays are becoming of interest as they reduce the frequency dependence of the feed/elements path length. Although synthesis algorithms can be extended from planar to conformal geometries, improving computational efficiency is not trivial. We present a POS, power pattern synthesis technique of conformal, shaped-beam reflectarrays, based on the p-series approach, on non-uniform FFTs, and on fast implementations of the FFT and of matrix-vector and vector-vector multiplications. The approach allows modulating computational burden and accuracy, depending on the needs. The method faces crucial issues concerning the reliability of the solution, by adopting a multi-step strategy. At first, the unknown phase shifts are represented by few degrees of freedom and an efficient and effective global optimisation algorithm is applied. Then, assuming as a starting point the obtained solution, all the reflectarray degrees of freedom are taken into account. The computational performance of the approach and its capability in synthesising shaped-beam patterns are discussed against parabolic and faceted reflectarrays, also considering the coverage of an operative mission.

关键词： parabolic reflectarrays reflectarray design frequency dependence reduction synthesis algorithms Optimisation techniques reflector antennas approximate scattering models conformal antennas p-series approach planar antenna arrays optimisation shaped-beam patterns Algebra vector-vector multiplications global optimisation algorithm phase-only synthesis fast Fourier transforms feed-elements path length phase shifts planar antennas shaped beam antennas Antenna arrays vectors fast Fourier transform Integral transforms nonuniform FFT faceted reflectarrays matrix-vector multiplications conformal reflectarrays matrix multiplication power pattern synthesis technique shaped-beam reflectarrays

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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

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INTEGRATION-THE VLSI JOURNAL 2012年第3期45卷 271-281页

作者： Kapadia, Nishit Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

The problem of VI-aware Network-on-Chip (NoC) design is extremely challenging, especially with the increasing core counts in today's power-hungry Chip Multiprocessors (CMPs). In this paper, we propose a novel framework for automating the synthesis of regular NoCs with Vls, to satisfy application performance constraints while minimizing chip power dissipation. Our proposed framework uses a set of novel algorithms and heuristics to generate solutions that reduce network traffic by up to 62%, communication power by up to 32%, and total chip power dissipation by up to 13%, compared to the best known prior work that also solves the same problem. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Networks-on-chip Voltage islands synthesis algorithms Chip multiprocessor Core-to-tile mapping

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A synthesis ENVIRONMENT FOR DESIGNING DSP SYSTEMS

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IEEE DESIGN & TEST OF COMPUTERS 1989年第2期6卷 35-44页

作者： CASAVANT, AE DABREU, MA DRAGOMIRECKY, M DUFF, DA JASICA, JR HARTMAN, MJ HWANG, KS SMITH, WD GE DEPT SIMULAT & CONTROL SYSTSCHENECTADYNY 12301

The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible architecture compilation environment), is to provide a set of algorithms that adequately support architecturally specific hardware synthesis for a class of DSP applications. They first identify the shortcomings of Parsifal, an earlier synthesis system, and discuss the requirements for FACE. They examine briefly the architectural issues. They then describe FACE's synthesis algorithms.<>

关键词： Multiprocessing Systems Circuit CAD Computer Architecture Digital Signal Processing Chips synthesis algorithms DSP Systems High Level synthesis Tool Throughput Requirements Digital Signal Processor FACE Flexible Architecture Compilation Environment Architecturally Specific Hardware synthesis Parsifal Digital Signal Processing Algorithm Design And Analysis Signal Processing algorithms Signal Design Hardware Signal synthesis Assembly Throughput Digital Signal Processing Chips Libraries

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OPTIMIZATIONS IN HIGH-LEVEL synthesis

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1986年第1-5期18卷 347-352页

作者： ROSENSTIEL, W UNIV KARLSRUHE INST INFORMAT 4D-7500 KARLSRUHEFED REP GER

Computer aided synthesis of circuit structures from behavioural level specifications has become a standard procedure in the design of integrated circuits. One disadvantage of several existing synthesis systems is their lack of efficiency with respect to chip area and processing speed. Within this paper several optimizations on different levels in the synthesis process are described. It is distinguished between data path and control part as well as between pure minimizations and optimization trade-offs.

关键词： Automatic synthesis of digital systems synthesis algorithms high level optimization integration of data path and control synthesis

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Controller synthesis for Mode-Target Games

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IFAC-PapersOnLine 2015年第27期48卷 343-350页

作者： Balkan, Ayca Vardi, Moshe Tabuada, Paulo UCLA Department of Electrical Engineering Los AngelesCA90095 United States Rice University Department of Computer Science HoustonTX77005 United States

Cyber-Physical Systems (CPS) are notoriously difficult to verify due to the intricate interactions between the cyber and the physical components. To address this difficulty, several researchers have argued that the synthesis paradigm is better suited to ensure the correct operation of CPS than the verification paradigm. The key insight of synthesis is that design should be constrained so that resulting systems are easily verified and, ideally, synthesis algorithms should directly provide a proof of correctness. In this paper we present a Linear Temporal Logic fragment inspired by specifications that frequently occur in control applications where we have a set of modes and corresponding targets to be reached for each mode. The synthesis problem for this fragment is formulated as a mode-target game and we show that these games can be solved in polynomial time by providing two embeddings of mode-target games into Generalized Reactivity(1) (GR(1)) games. While solving GR(1) games requires O(mnN2) symbolic steps when we have m assumptions, n guarantees, and a game graph with N states, mode-target games can be solved in O(nN2) symbolic steps when we have n modes and a game graph with N states. These embeddings, however, do not make full use of the specificity of mode-target games. For this reason we investigate in this paper a solution to mode-target games that does not rely on GR(1) embeddings. The resulting algorithm has the same worst case time complexity and we illustrate through experimental results the extent to which it improves upon the algorithms obtained via GR(1) embeddings. In doing so, we highlight the commonalities between mode-target games and GR(1) games while providing additional insight into the solution of GR(1) games. © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Computer circuits Controllers Embedded systems Formal methods Polynomial approximation Temporal logic Controller synthesis Cyber Physical System (CPS) Linear temporal logic Physical components Proof of correctness synthesis algorithms synthesis problems Time complexity

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STEPWISE TRANSFORMATION OF algorithms INTO ARRAY PROCESSOR ARCHITECTURES BY THE DECOMP

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VLSI DESIGN 1995年第1期3卷 67-80页

作者： VEHLIES, U Laboratorium für Informationstechnologie University of Hannover Schneiderberg 32 Germany

A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

关键词： COMPUTER AIDED synthesis synthesis algorithms CAD FOR ARCHITECTURE DESIGN STEPWISE TRANSFORMATION MAPPING METHODOLOGY DATA INDEPENDENT algorithms RUN TIME PROTOCOL NONREGULAR DEPENDENCE GRAPHS ARRAY PROCESSOR ARCHITECTURES

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INTEGRATED METHODOLOGY FOR SUPPORTING PACKET NETWORK PERFORMANCE MANAGEMENT AND PLANNING

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COMPUTER COMMUNICATIONS 1990年第9期13卷 558-570页

作者： WANG, JL WHITE, EA Bell Communications Research 3 Corporate Place Piscataway New Jersey 08854 USA

This paper describes an integrated approach for supporting packet network performance management and planning. As more and more packet networks — such as the public packet switched networks, common channel signalling networks and metropolitan area networks — are being deployed in the Regional Bell Operating Companies, new network operations systems are required for planning the evolution and engineering the service performance of these traffic-sensitive packet networks. This paper describes some of the synthesis and analysis algorithms that we have designed for supporting the traffic engineering of a public packet switched network. The synthesis algorithms include network element sizing, processor load balancing, network layer window size adjustment and traffic rerouting. The analysis algorithms include network element utilization and delay estimation as well as network end-to-end delay estimation.

关键词： analysis algorithms networks packet switching performance synthesis algorithms

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Classification of publications and models on transmission expansion planning

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IEEE TRANSACTIONS ON POWER SYSTEMS 2003年第2期18卷 938-946页

作者： Latorre, G Cruz, RD Areiza, JM Villegas, A Univ Ind Santander Grupo Invest & Sistemas Energia Elect Bucaramanga Colombia Univ Pontificia Bolivariana Inst Energia & Termodinam Medellin Colombia Interconex Elect SA Medellin Colombia

In this paper, the transmission planning state-of-the-art, which was obtained from the review of the most interesting models found in the international technical literature, is presented. The classification of publications was made, keeping in mind the solution methods, the treatment of the planning horizon, and the consideration of the new competitive schemes in the power sector., A discussion about the available tools for development of transmission planning models is also included.

关键词： bibliography review deregulation heuristic optimization mathematical programming modeling tools synthesis algorithms transmission planning state-of-the-art

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Supervisory Control of Timed Discrete-Event Systems Subject to Communication Delays and Non-FIFO Observations

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IFAC-PapersOnLine 2018年第7期51卷 456-463页

作者： Rashidinejad, Aida Reniers, Michel Feng, Lei Control Systems Technology Group Department of Mechanical Engineering Eindhoven University of Technology P.O.Box 513 EindhovenMB5600 Netherlands Department of Machine Design KTH Royal Institute of Technology Stockholm100 44 Sweden

Conventional supervisory control synthesis techniques are not adequate anymore when a network between the plant and the supervisor introduces communication delays. This paper presents a method to synthesize a networked supervisor handling delays in both observation and control channels. To deal with the problem of delayed observations, we propose an automaton modeling the behaviour of the plant observed by a supervisor through a network, called observed plant. In this automaton, events observed by a supervisor are delayed from those occurring in the plant. Moreover, since observation channels are considered not to have the first in first out (FIFO) characteristic, events may not be necessarily observed in the same order as they occurred within the plant. A safe, observable, controllable and nonblocking supervisor is synthesized for the observed plant by means of an adapted synthesis algorithm for timed discrete-event systems (TDES). By enabling the achieved supervisor to predict the effects of control delays, it will be further transformed to a networked supervisor. The networked supervisor makes decisions ahead of time to ensure that the commands will be applied on the right (plant) state. © 2018

关键词： Supervisory personnel Accident prevention Discrete event simulation Discrete time control systems synthesis (chemical) Communication delays Delayed observation Nonblocking supervisors nonblockingness Supervisory control Supervisory control synthesis synthesis algorithms Timed discrete event systems

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