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Proceedings of the ACM on Programming Languages

作者： Wang, Peixin Fu, Hongfei Chatterjee, Krishnendu Deng, Yuxin Xu, Ming Basics Lab Shanghai Jiao Tong University Shanghai China John Hopcroft Center for Computer Science Shanghai Jiao Tong University Shanghai China Klosterneuburg Austria Shanghai Key Laboratory of Trustworthy Computing East China Normal University China Center for Quantum Computing Pengcheng Laboratory Shenzhen China

The notion of program sensitivity (aka Lipschitz continuity) specifies that changes in the program input result in proportional changes to the program output. For probabilistic programs the notion is naturally extended to expected sensitivity. A previous approach develops a relational program logic framework for proving expected sensitivity of probabilistic while loops, where the number of iterations is fixed and bounded. In this work, we consider probabilistic while loops where the number of iterations is not fixed, but randomized and depends on the initial input values. We present a sound approach for proving expected sensitivity of such programs. Our sound approach is martingale-based and can be automated through existing martingale-synthesis algorithms. Furthermore, our approach is compositional for sequential composition of while loops under a mild side condition. We demonstrate the effectiveness of our approach on several classical examples from Gambler's Ruin, stochastic hybrid systems and stochastic gradient *** also present experimental results showing that our automated approach can handle various probabilistic programs in the literature. © 2020 Copyright held by the owner/author(s).

关键词： Stochastic systems Hybrid systems Expected Sensitivity Lipschitz continuity Martingales Number of iterations Probabilistic programs Sequential compositions Stochastic hybrid systems synthesis algorithms

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Supervisory Control of Timed Discrete-Event Systems Subject to Communication Delays and Non-FIFO Observations

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IFAC-PapersOnLine 2018年第7期51卷 456-463页

作者： Rashidinejad, Aida Reniers, Michel Feng, Lei Control Systems Technology Group Department of Mechanical Engineering Eindhoven University of Technology P.O.Box 513 EindhovenMB5600 Netherlands Department of Machine Design KTH Royal Institute of Technology Stockholm100 44 Sweden

Conventional supervisory control synthesis techniques are not adequate anymore when a network between the plant and the supervisor introduces communication delays. This paper presents a method to synthesize a networked supervisor handling delays in both observation and control channels. To deal with the problem of delayed observations, we propose an automaton modeling the behaviour of the plant observed by a supervisor through a network, called observed plant. In this automaton, events observed by a supervisor are delayed from those occurring in the plant. Moreover, since observation channels are considered not to have the first in first out (FIFO) characteristic, events may not be necessarily observed in the same order as they occurred within the plant. A safe, observable, controllable and nonblocking supervisor is synthesized for the observed plant by means of an adapted synthesis algorithm for timed discrete-event systems (TDES). By enabling the achieved supervisor to predict the effects of control delays, it will be further transformed to a networked supervisor. The networked supervisor makes decisions ahead of time to ensure that the commands will be applied on the right (plant) state. © 2018

关键词： Supervisory personnel Accident prevention Discrete event simulation Discrete time control systems synthesis (chemical) Communication delays Delayed observation Nonblocking supervisors nonblockingness Supervisory control Supervisory control synthesis synthesis algorithms Timed discrete event systems

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Broadband reconfigurable matching network using a non-uniform transmission line

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IET CIRCUITS DEVICES & SYSTEMS 2018年第5期12卷 615-619页

作者： Chen, Yen-Sheng Liu, Po-An Natl Taipei Univ Technol Dept Elect Engn Taipei 10608 Taiwan

In this study, the authors propose the use of distributed elements interconnected with switches to construct a reconfigurable matching network (RMN). Several RMNs are constructed using tunable lumped elements. However, this technique increases the system complexity because of the use of digital-to-analogue converters and synthesis algorithms. In this study, the proposed RMN employs a non-uniform transmission line with adjustable characteristic impedances, which are controlled by opening or closing the switches. While previous studies on non-uniform transmission lines have aimed to investigate the fixed configurations, this topology is designed to be an RMN that satisfies the design challenges. The maximum dimension is 0.2 times the guided wavelength of the low operational frequency, and five switches are used;however, the matchable impedances cover an extensive range of the Smith chart, and the RMN successfully tunes inherently unmatched antennas to operate at a target frequency band that depicts a fractional bandwidth of 60%. Additionally, the evaluated results depict that the fabricated RMN illustrates low insertion loss and high transducer gain and that it achieves both antenna-mismatch compensation and antenna-bandwidth extension.

关键词： digital-to-analogue converters transducer gain system complexity fractional bandwidth tunable lumped elements broadband antennas target frequency adjustable characteristic impedances unmatched antennas impedance matching digital-analogue conversion transmission lines insertion loss antenna-mismatch compensation antenna-bandwidth extension distributed elements nonuniform transmission line synthesis algorithms broadband reconfigurable matching network switches Smith chart low operational frequency RMN

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A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip synthesis

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ELECTRONICS 2016年第2期5卷 21-21页

作者： Bahirat, Shirish Pasricha, Sudeep Micron Technol Nonvolatile Engn Longmont CO 80501 USA Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

Network on Chip (NoC) architectures have emerged in recent years as scalable communication fabrics to enable high bandwidth data transfers in chip multiprocessors (CMPs). These interconnection architectures still need to conquer many challenges, e.g., significant power consumption and high data transfer latencies. Hybrid electro-photonic NoCs have been recently proposed as a solution to mitigate some of these challenges. However, with increasing application complexity, hardware dependencies, and performance variability, optimization of hybrid photonic NoCs requires traversing a massive design space. To date, prior work on software tools for rapid automated NoC synthesis have mainly focused on electrical NoCs. In this article, we propose a novel suite of software tools for effectively synthesizing hybrid photonic NoCs. We formulate and solve the synthesis problem using four search-based optimization heuristics: (1) Ant Colony Optimization (ACO);(2) Particle Swarm Optimization (PSO);(3) Genetic Algorithm (GA);and (4) Simulated Annealing (SA). Our experimental results show significant promise for the ACO and PSO based heuristics. Our novel implementation of PSO achieves an average of 64% energy-delay product improvements over GA and 53% improvement over SA;while our novel ACO implementation achieves 107% energy-delay product improvements over GA and 62% improvement over SA.

关键词： network-on-chip photonic interconnects synthesis algorithms chip multiprocessors

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Controller synthesis for Mode-Target Games

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IFAC-PapersOnLine 2015年第27期48卷 343-350页

作者： Balkan, Ayca Vardi, Moshe Tabuada, Paulo UCLA Department of Electrical Engineering Los AngelesCA90095 United States Rice University Department of Computer Science HoustonTX77005 United States

Cyber-Physical Systems (CPS) are notoriously difficult to verify due to the intricate interactions between the cyber and the physical components. To address this difficulty, several researchers have argued that the synthesis paradigm is better suited to ensure the correct operation of CPS than the verification paradigm. The key insight of synthesis is that design should be constrained so that resulting systems are easily verified and, ideally, synthesis algorithms should directly provide a proof of correctness. In this paper we present a Linear Temporal Logic fragment inspired by specifications that frequently occur in control applications where we have a set of modes and corresponding targets to be reached for each mode. The synthesis problem for this fragment is formulated as a mode-target game and we show that these games can be solved in polynomial time by providing two embeddings of mode-target games into Generalized Reactivity(1) (GR(1)) games. While solving GR(1) games requires O(mnN2) symbolic steps when we have m assumptions, n guarantees, and a game graph with N states, mode-target games can be solved in O(nN2) symbolic steps when we have n modes and a game graph with N states. These embeddings, however, do not make full use of the specificity of mode-target games. For this reason we investigate in this paper a solution to mode-target games that does not rely on GR(1) embeddings. The resulting algorithm has the same worst case time complexity and we illustrate through experimental results the extent to which it improves upon the algorithms obtained via GR(1) embeddings. In doing so, we highlight the commonalities between mode-target games and GR(1) games while providing additional insight into the solution of GR(1) games. © 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Computer circuits Controllers Embedded systems Formal methods Polynomial approximation Temporal logic Controller synthesis Cyber Physical System (CPS) Linear temporal logic Physical components Proof of correctness synthesis algorithms synthesis problems Time complexity

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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

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INTEGRATION-THE VLSI JOURNAL 2012年第3期45卷 271-281页

作者： Kapadia, Nishit Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA

The problem of VI-aware Network-on-Chip (NoC) design is extremely challenging, especially with the increasing core counts in today's power-hungry Chip Multiprocessors (CMPs). In this paper, we propose a novel framework for automating the synthesis of regular NoCs with Vls, to satisfy application performance constraints while minimizing chip power dissipation. Our proposed framework uses a set of novel algorithms and heuristics to generate solutions that reduce network traffic by up to 62%, communication power by up to 32%, and total chip power dissipation by up to 13%, compared to the best known prior work that also solves the same problem. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Networks-on-chip Voltage islands synthesis algorithms Chip multiprocessor Core-to-tile mapping

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Fast phase-only synthesis of conformal reflectarrays

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IET MICROWAVES ANTENNAS & PROPAGATION 2010年第12期4卷 1989-2000页

作者： Capozzoli, A. Curcio, C. D'Elia, G. Liseno, A. Univ Naples Federico II DIBET I-80125 Naples Italy

Phase-only synthesis (POS) techniques represent an important tool for reflectarray design. Indeed, although based on approximate scattering models, for planar antennas, they are numerically effective thanks to the use of fast Fourier transform (FFT) routines. Conformal reflectarrays are becoming of interest as they reduce the frequency dependence of the feed/elements path length. Although synthesis algorithms can be extended from planar to conformal geometries, improving computational efficiency is not trivial. We present a POS, power pattern synthesis technique of conformal, shaped-beam reflectarrays, based on the p-series approach, on non-uniform FFTs, and on fast implementations of the FFT and of matrix-vector and vector-vector multiplications. The approach allows modulating computational burden and accuracy, depending on the needs. The method faces crucial issues concerning the reliability of the solution, by adopting a multi-step strategy. At first, the unknown phase shifts are represented by few degrees of freedom and an efficient and effective global optimisation algorithm is applied. Then, assuming as a starting point the obtained solution, all the reflectarray degrees of freedom are taken into account. The computational performance of the approach and its capability in synthesising shaped-beam patterns are discussed against parabolic and faceted reflectarrays, also considering the coverage of an operative mission.

关键词： parabolic reflectarrays reflectarray design frequency dependence reduction synthesis algorithms Optimisation techniques reflector antennas approximate scattering models conformal antennas p-series approach planar antenna arrays optimisation shaped-beam patterns Algebra vector-vector multiplications global optimisation algorithm phase-only synthesis fast Fourier transforms feed-elements path length phase shifts planar antennas shaped beam antennas Antenna arrays vectors fast Fourier transform Integral transforms nonuniform FFT faceted reflectarrays matrix-vector multiplications conformal reflectarrays matrix multiplication power pattern synthesis technique shaped-beam reflectarrays

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Designing on FPGA for improved performance

Designing on FPGA for improved performance

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9th International Multitopic Conference of Pakistan

作者： Baig, Muhammad Iram Sharif, Atif Sheikh, Inamul Hassan Univ Engn & Technol Taxila Pakistan

ISBN: (纸本)9780780394292

The area of Field Programmable Gate array (FPGA) design is evolving at a rapid pace. Advancements in the complexity of the FPGA's architecture mean that now it can be used in far more applications than before. This paper presents synthesis process, synthesis algorithm requirements and various other design improvements which in a true sense enhance the digital system performance with respect to area and delay trade offs. It. also covers a number of timing issues that are important in basic digital system design. The issues are normally observed while working with Xilinx FPGAs. Some established techniques are reviewed relative to these criteria to understand their applicability, and the potential for further research in these specialized areas.

关键词： synthesis algorithms synchronous and as asynchronous design clock gating clock skews clocking strategies

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Classification of publications and models on transmission expansion planning

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IEEE TRANSACTIONS ON POWER SYSTEMS 2003年第2期18卷 938-946页

作者： Latorre, G Cruz, RD Areiza, JM Villegas, A Univ Ind Santander Grupo Invest & Sistemas Energia Elect Bucaramanga Colombia Univ Pontificia Bolivariana Inst Energia & Termodinam Medellin Colombia Interconex Elect SA Medellin Colombia

In this paper, the transmission planning state-of-the-art, which was obtained from the review of the most interesting models found in the international technical literature, is presented. The classification of publications was made, keeping in mind the solution methods, the treatment of the planning horizon, and the consideration of the new competitive schemes in the power sector., A discussion about the available tools for development of transmission planning models is also included.

关键词： bibliography review deregulation heuristic optimization mathematical programming modeling tools synthesis algorithms transmission planning state-of-the-art

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synthesis of clock tree topologies to implement nonzero clock skew schedule

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1999年第6期146卷 321-326页

作者： Kourtev, IS Friedman, EG Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

Designing the topology of a clock distribution network is considered for a synchronous digital integrated circuit so as to satisfy a nonzero clock skew schedule. A methodology and related algorithms for synthesising the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming problem. The approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to 64% performance improvement is attained on these circuits by exploiting nonzero clock skew throughout the synchronous system. Clock tree topologies that implement the nonzero clock skew schedule based on the synthesis algorithms presented are described for each of the benchmark circuits.

关键词： clocks clock distribution network synthesis algorithms VLSI circuit timing information ISCAS'89 benchmark circuits integer programming integer linear programming problem nonzero clock skew schedule synchronous digital integrated circuit timing integrated circuit design linear programming logic CAD clock tree topologies

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