A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic spec...
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A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.
This paper describes an integrated approach for supporting packet network performance management and planning. As more and more packet networks — such as the public packet switched networks, common channel signalling...
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This paper describes an integrated approach for supporting packet network performance management and planning. As more and more packet networks — such as the public packet switched networks, common channel signalling networks and metropolitan area networks — are being deployed in the Regional Bell Operating Companies, new network operations systems are required for planning the evolution and engineering the service performance of these traffic-sensitive packet networks. This paper describes some of the synthesis and analysis algorithms that we have designed for supporting the traffic engineering of a public packet switched network. The synthesis algorithms include network element sizing, processor load balancing, network layer window size adjustment and traffic rerouting. The analysis algorithms include network element utilization and delay estimation as well as network end-to-end delay estimation.
The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible...
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The authors describe a high-level synthesis tool that addresses the broad range of throughput requirements inherent in all DSP (digital signal processor) systems. The primary role of this system, called FACE (flexible architecture compilation environment), is to provide a set of algorithms that adequately support architecturally specific hardware synthesis for a class of DSP applications. They first identify the shortcomings of Parsifal, an earlier synthesis system, and discuss the requirements for FACE. They examine briefly the architectural issues. They then describe FACE's synthesis algorithms.<>
Computer aided synthesis of circuit structures from behavioural level specifications has become a standard procedure in the design of integrated circuits. One disadvantage of several existing synthesis systems is thei...
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Computer aided synthesis of circuit structures from behavioural level specifications has become a standard procedure in the design of integrated circuits. One disadvantage of several existing synthesis systems is their lack of efficiency with respect to chip area and processing speed. Within this paper several optimizations on different levels in the synthesis process are described. It is distinguished between data path and control part as well as between pure minimizations and optimization trade-offs.
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