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Assertion-Based Verification of I2C Module Using systemverilog

ELECTRONICS 2025年第8期14卷

作者： Moon, Dae-Won Pyo, Seung-Hyun Hong, Dae-Ki Bataa, Otgonbayar Norinpel, Erdenekhuu Sangmyung Univ Dept Elect Informat Syst Engn Cheonan 31066 South Korea Sangmyung Univ Dept Syst Semicond Engn Cheonan 31066 South Korea Mongolian Univ Sci & Technol Sch Informat & Commun Technol Ulaanbaatar 14191 Mongolia

In today's semiconductor verification field, systemverilog Assertions (SVAs) are one of the most important methodologies for functional verification. A representative verification technique is Universal Verification Methodology (UVM)-based verification, which utilizes a systemverilog class library. On the other hand, Assertion-Based Verification (ABV) using SVA allows hardware designs to be verified without requiring knowledge of systemverilog's Object-Oriented Programming (OOP) concepts or UVM. Its syntax is intuitive and concise, enabling rapid detection of RTL (Register Transfer Level) bugs during the design and verification phases. This methodology significantly enhances productivity by drastically reducing the time required for semiconductor development. This paper proposes an ABV verification environment using SVA that is reusable in other verification environments for verifying the main functions of the Inter-Integrated Circuit (I2C), one of the serial synchronous communication protocols. Finally, through the development of the RTL design and simulation of the core functionalities of I2C, the key characteristics of I2C were verified using ABV with SVA.

关键词： ABV SVA systemverilog assertion concurrent assertion UVM I2C

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systemverilog Modeling of SFQ and AQFP Circuits

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2020年第2期30卷

作者： Tadros, Ramy N. Fayyazi, Arash Pedram, Massoud Beerel, Peter A. Univ Southern Calif Los Angeles CA 90007 USA

Exascale computing and its associated increasingly massive amounts of data require increasingly efficient computing platforms;and semiconductor technology is struggling to keep up. Meanwhile, superconducting electronics (SCE) is increasingly gaining interest in both industry and academia as a serious contender to replace silicon for supercomputing. In particular, non-resistively biased single-flux quantum (SFQ) circuits have a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude of higher speed, and adiabatic quantum-flux-parametron (AQFP) circuits possess a theoretical potential of six orders of magnitude reduction in power when compared to the state-of-the-art semiconductor circuits. Unfortunately, the SCE community lacks a reliable design flow. Rather than creating a complete design flow from scratch, it is often more efficient to reuse well-established semiconductor tool flows developed by EDA companies that have benefited from research and development over the past half-century. One of the components of this flow is the hardware description language (HDL) modeling of gates for behavioral and functional simulation of large netlists. The previous HDL models proposed for SCE lack modularity are not compatible with existing CMOS standards, and are overly complex. This article presents System Verilog models for SFQ and AQFP gates and the circuits that interface between them. Our models are compatible with standard delay format and commercial simulators. They offer a generalizable modular debugging platform, are elegant and conceptual, and can capture many circuit parameters, environmental effects, and advanced SCE phenomena.

关键词： Adiabatic quantum-flux-parametron (AQFP) hardware description language (HDL) RSFQ single-flux quantum (SFQ) systemverilog Verilog

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systemverilog implicit port enhancements accelerate system design & verification

SystemVerilog implicit port enhancements accelerate system d...

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45th ACM/IEEE Design Automation Conference

作者： Cummings, Clifford E. Sunburst Design Inc Beaverton OR 97005 USA

ISBN: (纸本)9781605581156

The IEEE Std 1800-2005 systemverilog Standard added new implicit port instantiation enhancements that help accelerate toplevel composition of large ASIC & FPGA Designs. This paper details the new .* and .name implicit port instantiation capabilities, the rules related to the use of these new enhancements, and how these enhancements offer concise RTL coding styles while enforcing stronger port-type checking.

关键词： systemverilog instantiation implicit ports . name Verilog EMACS mode Verilog

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Design and Verification of a SAR ADC systemverilog Real Number Model

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2024年第3期40卷 315-328页

作者： Georgoulopoulos, Nikolaos Mamali, Theodora Hatzopoulos, Alkis Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki Greece

Mixed-signal applications have emerged as a significant trend in the semiconductor industry, with considerable efforts directed towards developing fast and accurate designs that integrate both analog and digital components. However, mixed-signal verification presents a major challenge due to the slow verification time and limited robustness of traditional verification techniques. In this study, a verification architecture for a successive-approximation register (SAR) analog-to-digital converter (ADC) real number model (Real Number Modeling - RNM) using systemverilog is presented, which utilizes an efficient UVM-based methodology. The proposed approach combines the UVM capabilities with the RNM model of the SAR ADC to generate a reusable, fast, and robust verification environment with a reduced time-to-market. The testbench creation and simulation were carried out using Cadence Xcelium. The proposed verification architecture employs constrained-random stimulus generation, analog assertions, and coverage metrics to enhance verification effectiveness. Additionally, aim of this work is to emphasize on the RNM efficiency with systemverilog, and apply its modeling capabilities for a SAR ADC. The presented real number model was compared to a Verilog-AMS model. The conducted experiments provided evidence that the proposed RNM model exhibits a significant improvement in simulation efficiency compared to previous works documented in the literature (simulation time was at 0.5 s, compared to a Verilog-AMS reference model's simulation at 20 s). This improvement in efficiency is achieved without compromising on the accuracy of the simulation, ensuring that the model maintains a satisfactory level of precision.

关键词： Analog-to-digital converter Functional verification Real number modeling Successive-approximation register systemverilog

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systemverilog UVM-based Verification Environment for a SpaceFibre Router 9

SystemVerilog UVM-based Verification Environment for a Space...

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9th International SpaceWire and SpaceFibre Conference (ISC)

作者： Gigli, Lorenzo Nannipieri, Pietro Zulberti, Luca Vagaggini, Simone Fanucci, Luca Univ Pisa Dept Informat Engn Via Caruso 16 I-56122 Pisa Italy IngeniArs Srl Via Ponte Piglieri 8 I-56121 Pisa Italy

ISBN: (纸本)9780995453029

The number of space missions has seen continuous growth in the last years. Accordingly, satellite communications traffic and onboard spacecraft technologies have also increased. To manage high data flows in high-bandwidth communication protocols the European Cooperation for Space Standardization has released the SpaceFibre protocol in 2019, whose features for data handling and the introduction of routing capabilities increase the complexity of the infrastructures in such networks. Consequently, a crucial implementation step towards the realisation of a satellite high speed data-handling network is the design and the verification of a routing switch at different levels. As far as the network layer is concerned, the literature and the market lack verification environments for this type of devices. This work proposes a reusable and customisable network-level verification environment for SpaceFibre routing switches, that leverages the capabilities of systemverilog and the Universal Verification Methodology standard. In particular, the environment can be connected with any network topology, verifying any router individually. Furthermore, our environment requires network-level compatibility with the hardware interfaces, being independent from the implemented data-layer.

关键词： SpaceFibre Router Network-Layer Verification Universal Verification Methodology (UVM) systemverilog

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PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in systemverilog

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2015年第8期62卷 1908-1917页

作者： Jang, Jieun Kim, Jaeha Seoul Natl Univ Inter Univ Semicond Res Ctr Sch Elect Engn & Comp Sci Seoul 151744 South Korea

This paper presents an event-driven simulation methodology for injection-locked oscillators. The proposed method adopts a phase-domain macromodel based on a perturbation projection vector (PPV), which expresses the oscillator's phase response using a nonlinear, time-varying differential equation. By expressing the PPV using a piecewise polynomial function, the PPV model can be simulated in an event-driven fashion on a digital logic simulator like systemverilog. While this piecewise polynomial approximation introduces a trade-off between the simulation accuracy and speed, our results show that the simulation accuracy quickly reaches its optimal value as the piecewise interval number increases even with first-order polynomials. The experimental results with an LC oscillator, ring oscillator, and burst-mode CDR models operating with both periodic and aperiodic inputs demonstrate that the proposed models achieve speeds up to 2 similar to 30x that of transistor-level Spectre simulations with the same accuracy.

关键词： Event-driven simulation injection-locked oscillator perturbation projection vector systemverilog

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Parameterizable Real Number Models for Mixed-Signal Designs Using systemverilog

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2021年第5-6期37卷 685-700页

作者： Georgoulopoulos, Nikolaos Hatzopoulos, Alkiviadis Aristotle Univ Thessaloniki Dept Elect & Comp Engn Thessaloniki Greece

Nowadays, the semiconductor industry directs its attention to mixed-signal System-on-Chip (SoC) applications. Main targets are the creation of accurate and fast mixed-signal SoC designs, composed of both digital and analog components, and the reduction of time to market for this kind of integrated circuits (ICs). In order to bring a mixed-signal SoC faster to the market, higher system-level simulation speed is required, with respect to traditional modeling approaches. Real Number Modelling (RNM) could be an effective solution. In this work, a sigma-delta analog-to-digital converter (ADC), a voltage-controlled oscillator (VCO) and a digital phase-locked loop (PLL) are implemented as real number models using systemverilog. This paper is an extended version of work previously published by the authors. Herein, more accurate and parameterizable models were created, while their validation process is analyzed and achieved using a novel metric for accuracy estimation. The proposed models' parameterizability enhances the usability of the models to various SoC designs. Aim of this work is to underline the RNM effectiveness provided by systemverilog, and exhibit a way to apply RNM for modeling and simulation of widely used analog/mixed-signal (AMS) blocks. The presented real number models were compared to Verilog-A, Verilog-AMS, and transistor-level SPICE models. All tests showed that the proposed real number models based on systemverilog demonstrate noteworthy improvement on simulation efficiency, with respect to previous works in the literature, preserving simultaneously sufficient accuracy.

关键词： Analog-to-digital converter Mixed-signal design Real number modeling Phase-locked loop systemverilog

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systemverilog-based Verification Environment using SystemC Custom Hierarchical Channel

SystemVerilog-based Verification Environment using SystemC C...

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IEEE 8th International Conference on ASIC

作者： You, Myoung-Keun Song, Gi-Yong Chungbuk Natl Univ Coll Elect & Comp Engn Comp Engn Div Cheongju 361763 South Korea Chungbuk Natl Univ Coll Elect & Comp Engn Elect Engn Div Cheongju 361763 South Korea

ISBN: (纸本)9781424438686

A verification environment which is based on a constrained random layered testbench using System Verilog OOP is implemented in this paper to verify, the functionality of DUT designed with synthesizable constructors of System Verilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that combine the properties of two or more class types. Because System Verilog OOP technique does not allow multiple inheritance, we adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the systemverilog-based layered testbench using System Verilog DPI and ModelSim macro. System Verilog DPI provides a way to interface with any other foreign language. Functions and tasks registered to shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit. In order to simulate SystemC design unit with ModelSim, the SystemC design unit should be modified using some macros provided by ModelSim. In this paper, FIFO channel frequently used in high-level communication is designed as a custom hierarchical channel which has three base classes;sc_channel, channel interface, and data payload interface. The low-layer components of the System Verilog-based layered test bench communicate with DUT using virtual interface, and other components can communicate with each other using FIFO channel. DUT in this paper includes BFM because most IPs designed for SoC are connected to a bus and controlled through the bus(1).

关键词： systemverilog SystemC verification environment layered-testbench custom hierarchical channel

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A model-driven framework for design and verification of embedded systems through systemverilog

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2019年第3-4期23卷 179-223页

作者： Anwar, Muhammad Waseem Rashid, Muhammad Azam, Farooque Kashif, Muhammad Butt, Wasi Haider NUST CEME Dept Comp & Software Engn Islamabad Pakistan Umm Al Qura Univ Comp Engn Dept Mecca Saudi Arabia Istanbul Sehir Univ Dept Elect & Comp Engn Istanbul Turkey

The demands of system complexity and design productivity for embedded systems can be managed by simplifying and reusing the design. Furthermore, these systems should be verified as early as possible in the development process to reduce the cost and effort. The rationale of the proposed framework in this article is to simplify the design and verification process of embedded systems in the context of Model Based System Engineering (MBSE). To achieve this, UML profile for systemverilog (UMLSV) is proposed to model the design and verification requirements. Particularly, we introduce various UMLSV stereotypes to model the system design (structure and behavior). Furthermore, a temporal extension of Object Constraint Language is used to capture the verification requirements (properties/constraints) in UMLSV. Consequently, the proposed framework allows the modeling of system design (structure and behavior) along with the verification aspects at higher abstraction level. Following the MBSE process, the high-level models and the verification constraints are transformed into synthesizable systemverilog Register Transfer Level and systemverilog Assertions code. This leads to perform the Assertions Based Verification of system design in the early development phases by using state-of-the-art simulators. The effectiveness of the proposed framework is demonstrated with the help of multiple case studies including Traffic Lights Controller, Unmanned Aerial Vehicle, Elevator and Car Collision Avoidance System.

关键词： Model-driven framework UMLSV Embedded systems systemverilog

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V2Va+: An Efficient systemverilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS

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IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS 2024年 5卷 387-397页

作者： Wang, Chao Shao, Yicong Huang, Jiajie Lu, Wangzilu Gu, Zhiwen Li, Longfan Zhang, Yuhang Zhao, Jian Mao, Wei Li, Yongfu Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai 200240 Peoples R China Xidian Univ Hangzhou Inst Technol Hangzhou 311231 Peoples R China

This paper introduces a streamlined systemverilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable systemverilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and digital circuits. Through a set of mapping rules, V2Va + facilitates mixed-signal simulations in an analog environment, negating the requirement for a separate mixed-signal simulation engine and overcoming multiple types of EDA licensing obstacles. The V2Va + translation tool comprises two integral components: a parser function, tasked with extracting information from systemverilog and Verilog files, and a Verilog-A generator, responsible for generating corresponding Verilog-A code. V2Va + excels in handling complexity, ensuring accuracy, and improving efficiency. It effectively manages a wide range of design complexities, maintains functional consistency during translation, and significantly reduces simulation time, achieving speed-ups of over 2x. These strengths underscore its significant impact and applicability in the domain of circuit design.

关键词： Translation Codes Runtime Design methodology Syntactics Generators Complexity theory Hardware design languages Engines Digital circuits Verilog-A Verilog systemverilog mixed-signal simulation abstract syntax tree translator

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