检索结果-内蒙古大学图书馆

IEEE Instrumentation and Measurement Technology Conference

作者： Xuefeng Dai Jun Gu Peng Ye Yu Zhao Kuojun Yang Department of Automation Engineering University of Electronic Science and Technology of China China

ISBN: (数字)9781728144603

ISBN: (纸本)9781728144610

In order to realize the flexibility of real-time digital signal processing system. This paper presents a novel parallel Frequency Impulse Response (FIR) filter structure based on Combined systolic Arrays (CSAs). CSAs are associated with the polyphase decomposition of parallel FIR structure which can suitable for dedicate arithmetic - Convolution in a real-time system. Based on Look Up Tables (LUTs) in Field Programmable Gate Array (FPGA), it is flexible to configure different coefficient order and path of parallel as the cascade characteristic of the CSAs. The proposed structure is validated via an FIR bandpass filter and a fractional delay filter in an FPGA (Xilinx, XC7325T). The implementation results indicate that the proposed structure can guarantee the high efficiency of the real-time system and realize the Hardware-Flexible.

关键词： Field Programmable Gate Array (FPGA) Parallel FIR Combined systolic Arrays Field programmable gate arrays real-time systems delay filters FIR filters systolic algorithms proposed structure time system FARP2 gene PUF60 gene parallel configuration Parallel Lines

来源：评论

学校读者我要写书评

暂无评论

Design of systolic Array Multiplier Circuit using Reversible Logic

Design of Systolic Array Multiplier Circuit using Reversible...

引用

IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology

作者： Chinthaparthi Madhulika V. Shiva Prasad Nayak Chaluvadi Prasanth Tumma Hemanth Sai Praveen Dept. of ECE GITAM University Reddy Dept. of ECE GITAM University

ISBN: (纸本)9781509037056

For data transmission, an ideal communication relies on Low Power Design. systolic array multiplier with the reversible logic is widely known among those techniques for synchronizing signals in DSP processor applications. Low power circuit design yields many favorable conditions like increased performance, system capacity, minimized cost etc. Reversible logic is a phenomenal approach to reduce heat dissipation and information loss. Among basic arithmetic operations, Multiplication demands more processing time and seek complex hardware. As Conventional systolic Array Multiplier is designed using irreversible logic gates, there is undesired power dissipation. So, to improvise this downside, this paper illuminates the design of low power systolic Array Multiplier using reversible logic gates which performs data processing in Parallelism manner [5]. Power, delay, garbage outputs and quantum cost is calculated mathematically in this paper. Finally, Cadence Virtuoso is used to obtain simulation results. 2.8μw is the power for the proposed design when the power of individual components.

关键词： Garbage Outputs (GO) Quantum Cost (QC) Multiplier cell(MC) Peres Full Adder (PFA) Peres gate (PG) Toffoli gate(TG) systolic algorithms Energy sources Multiplying circuits information loss HEAT DISSIPATION Formal logic data transmission CIRCUIT DESIGN power Power LOW POWER Logic gates Power (Psychology)

来源：评论

学校读者我要写书评

暂无评论

Shape Reconstruction using Instruction systolic Array

Shape Reconstruction using Instruction Systolic Array

引用

IEEE Sensors Conference

作者： Partheepan Kandaswamy James A. Flint Vassilios A. Chouliaras Wolfson School of Mechanical Electrical and Manufacturing Engineering Loughborough University Loughborough LE11 3TU UK

ISBN: (纸本)9781509010134

This paper describes a novel, 2D mesh architecture prototype based on the Instruction systolic Array (ISA) paradigm for distributed computing on fabrics. We discuss a real-time shape sensing and reconstruction application executing on this architecture and demonstrate a physical design for a wearable system based on the ISA concept constructed from off-the-shelf microcontrollers and sensors. Results demonstrate the application executes in 39 ms the prototype ISA implementation thus confirming the viability of the proposed architecture for fabric-resident computing devices.

关键词： Instruction systolic Array distributed sensor networks System on fabrics wearable electronics fabric-resident computing device shape reconfiguration systolic algorithms Wearable computers Sensor networks instruction ARCHITECTURE Building construction Distributed computing Textile fabrics fabric

来源：评论

学校读者我要写书评

暂无评论

An FPGA-Based systolic Array to Accelerate the BWA-MEM Genomic Mapping Algorithm 15

An FPGA-Based Systolic Array to Accelerate the BWA-MEM Genom...

引用

International Conference on Embedded Computer Systems Architectures Modeling and Simulation

作者： Houtgast, Ernst Joachim Sima, Vlad-Mihai Bertels, Koen Al-Ars, Zaid Delft Univ Technol Fac EEMCS Delft Netherlands

ISBN: (纸本)9781467373111

We present the first accelerated implementation of BWA-MEM, a popular genome sequence alignment algorithm widely used in next generation sequencing genomics pipelines. The Smith-Waterman-like sequence alignment kernel requires a significant portion of overall execution time. We propose and evaluate a number of FPGA-based systolic array architectures, presenting optimizations generally applicable to variable length Smith-Waterman execution. Our kernel implementation is up to 3x faster, compared to software-only execution. This translates into an overall application speedup of up to 45%, which is 96% of the theoretically maximum achievable speedup when accelerating only this kernel.

关键词： systolic algorithms execution time acceleration Genomics Sequence Alignment Seeds Speeding array structure Legal Executions Kernel

来源：评论

学校读者我要写书评

暂无评论

A novel fast algorithm for the pseudo Winger-Ville distribution

引用

JOURNAL OF COMMUNICATIONS TECHNOLOGY AND ELECTRONICS 2015年第11期60卷 1238-1247页

作者： Hua, X. Liu, J. Wuhan Inst Technol Sch Elect & Informat Engn Lab Image Proc Wuhan 430205 Hubei Province Peoples R China Huazhong Univ Sci & Technol Inst Sch Automat Natl Key Lab Sci & Technol Multispectral Informat Wuhan 430074 Hubei Province Peoples R China

A novel approach to Discrete Wigner-Ville Distribution (DWVD) is proposed in this paper. Unlike the conventional methods, the computation of Discrete Wigner-Ville Distribution is transformed to the computation of the first-order moments by the simple mathematical deduction. A scalable and efficient systolic array is designed to implement this approach. There are several advances in our algorithm such as the avoidance of multiplications, the simple computation structure and only integer additions. Although many additions required, the proposed algorithms is simple and more applicable.

关键词： Pseudo DEDUCTION Fasting Novels algorithms systolic algorithms Avoidance

来源：评论

学校读者我要写书评

暂无评论

Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array

Hardware acceleration for the banded Smith-Waterman algorith...

引用

12th International Conference on Field-Programmable Technology (FPT)

作者： Chen, Peng Wang, Chao Li, Xi Zhou, Xuehai Univ Sci & Technol China Dept Comp Sci Hefei 230026 Peoples R China

ISBN: (纸本)9781479921980;9781479921997

The Smith-Waterman is one of the most popular algorithms in the molecular sequence alignment. It is often used to find the best local alignment between two strings by calculating the similarity score of the pair of strings. The algorithm is of great potential to be parallelized and has been employed by a lot of FPGA-based solutions, mostly with the systolic array manner. However, the architecture designers always find the number of the process elements (PE) in their implementation quite limited by the resources available on the FPGA devices. They either make decomposition or fold the implementation of their applications when facing a large requirement for the process elements number. In this paper, we put forward a novel FPGA-based architecture which could address the problem with a bounded number of PEs to realize any lengths of systolic array. It is mainly based on the idea of the banded Smith-Waterman but with a key distinguish that it reuses the PEs which are beyond the boundary. Analysis shows that the approach is as fast as the normal systolic fabric and obtains quite considerable resource reduction.

关键词： systolic algorithms Sequence Alignment Cosmic strings

来源：评论

学校读者我要写书评

暂无评论

FPGA Architecture for Fast Floating Point Matrix Inversion Using Uni-dimensional systolic Array Based Structure

FPGA Architecture for Fast Floating Point Matrix Inversion U...

引用

IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

作者： Ondrej Hnilicka Technical University of Liberec

ISBN: (纸本)9781467361354

This paper describes the structure of fast matrix inversion on FPGA. The structure is derived from the systolic array algorithm and revised to the uni-dimensional array to lower the resources consumption for practical use. Input matrix, with single precision floating point elements, is inverted in 5n2+4n-3 time ticks. Both mantissa and exponent processing units are proposed to be easily implemented on FPGA. Comparison of the structure with inversion using MicroBlaze soft CPU is presented.

关键词： FPGA Matrix inversion systolic array matrix inversion systolic algorithms Field programmable gate arrays Resource utilization Mantissa FLOATING POINTS

来源：评论

学校读者我要写书评

暂无评论

A Practical Measure of FPGA Floating Point Acceleration for High Performance Computing

A Practical Measure of FPGA Floating Point Acceleration for ...

引用

IEEE International Conference on Application-specific Systems, Architectures and Processors

作者： John D. Cappello Dave Strenski Optimal Design Inc. Sewell NJ Cray Inc. Ypsilanti Michigan

ISBN: (纸本)9781479904945

A key enabler for Field Programmable Gate Arrays (FPGAs) in High Performance Computing (HPC) has been the addition of hard arithmetic cores. These "slices of DSP" dedicated to accelerated number crunching allow FPGAs to deliver more computing muscle, especially for floating point algorithms. This paper compares how an FPGA's performance in a practical HPC application measures up to its theoretical capacity. The implementation of a floating point matrix multiplication algorithm based on a 12x12 MAC (Multiply-Accumulate) array targeting the Xilinx Virtex 7 XT family is described. Several design techniques were used to ensure uninterrupted systolic operation of the array throughout execution, including a novel approach to handling heavily pipelined accumulators, as well as a scheme for overcoming the inherent inefficiencies of DDR3 memory. The result is a sustained "practical" performance range of 144-180 GFLOPS, compared to the target device's "theoretical" range of 257-290 GFLOPS.

关键词： FPGA matrix multiplication high performance computing floating point arithmetic multiply-accumulate systolic array hardware acceleration GFLOPS Xilinx Virtex-7 DSP48 heavily-pipelined accumulators High Performance Computing Field programmable gate arrays floating point arithmetic Matrix multiplication systolic algorithms FLOATING POINTS Digital arithmetic target device

来源：评论

学校读者我要写书评

暂无评论

FPGA based Architectures for High Performance Adaptive FIR Filter Systems

FPGA based Architectures for High Performance Adaptive FIR F...

引用

IEEE International Instrumentation and Measurement Technology Conference

作者： Sufeng Niu Semih Aslan Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago IL 60616 U.S.A. SMART Lab Ingram School of Engineering Texas State University San Marcos TX 78666 USA

ISBN: (纸本)9781467346214

In this paper, we present a high performance adaptive FIR filter hardware architecture. In particular, the RLS (Recursive Least Square) algorithm for adaptive signal processing is explored based on QR decomposition, which is accomplished by using the Givens Rotation algorithm. The Givens Rotation algorithm is implemented using a systolic array and LUT-based Newton's method. This architecture is suitable for high-speed FPGAs or ASIC designs. It also solves the tradeoff between throughput and latency issues. As a case study, this QR design is tested using Xilinx XC5VLX110T FPGA. The findings show that the system is capable of running the QR decomposition at up to 200MHz with 56 clock cycles latency.

关键词： FIR FPGAs ASIC ASIC application specific integrated circuits FIR filters FARP2 gene PUF60 gene Field programmable gate arrays adaptive FIR filter Newton method quick release systolic algorithms adaptive signal processing Latency HIGH-PERFORMANCE ARCHITECTURE tradeoffs

来源：评论

学校读者我要写书评

暂无评论

Approximate Matrix Inversion for High-Throughput Data Detection in the Large-Scale MIMO Uplink

Approximate Matrix Inversion for High-Throughput Data Detect...

引用

IEEE International Symposium on Circuits and Systems

作者： Michael Wu Bei Yin Aida Vosoughi Christoph Studer Joseph R. Cavallaro Chris Dick Rice University Houston TX USA Xilinx San Jose CA USA

ISBN: (纸本)9781467357609

The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose--to the best of our knowledge--first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity. We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference FPGA implementation results for various system configurations. For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 1.9 M matrices/s on a Xilinx Virtex-7 FPGA, while using only 3.9% of the available slices and 3.6% of the available DSP48 units.

关键词： large-scale MIMO best matrix inversion multiple input multiple output systems data detection large sizes systolic algorithms ANTENNA up link Design flow Approximate

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：