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systolic algorithms FOR RECTILINEAR POLYGONS

COMPUTER-AIDED DESIGN 1987年第1期19卷 15-24页

作者： KANE, R SAHNI, S UNIV MINNESOTA DEPT COMP SCIMINNEAPOLISMN 55455

We develop systolic algorithms for the OR, AND, Oversizing, and Undersizing of rectilinear polygons. These algorithms work on an edge representation of the polygons rather than on a bit map representation. The algorithms are to be run on a systolic chain of processors. The edges are input at the left end of this chain. From here, they ‘float’ as far to the right as necessary. As edges float to the right, they compare themselves with edges that are resident in the processors they are floating through. During this comparison the output polygons are generated. Output polygons float to the left. These polygons are output from the left end of the chain. The throughput of the systolic system can be improved by increasing the length of the processor chain.

关键词： rectilinear polygons systolic algorithms oversize undersize circuit design

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TRANSLATING FROM FP TO OCCAM FOR systolic algorithms

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MICROPROCESSORS AND MICROSYSTEMS 1991年第8期15卷 435-444页

作者： LIN, YC Department of Electronic Engineering National Taiwan Institute of Technology Taipei Taiwan 106 Republic of China

Programming multiprocessor systems is not a simple task and is often error-prone. In particular, programming a message-passing parallel computer usually demands large amounts of work in development and debugging to avoid deadlock. It is, therefore, essential to have software to support the task of parallel programming, or more desirably to have automatic parallel program generators to greatly reduce the labour. In this paper, we present a novel method of automatically generating Occam programs;or more precisely, we present an automatic FP-to-Occam translator called AFO. Occam is a parallel, message-passing programming language executed on a network of processors called transputers, but is basically a sequential language extended with primitive parallel and communication constructs. In contrast, FP is a functional language that contains no communication details and supports parallel thinking naturally with higher-level parallel constructs. FP has been used to derive many systolic algorithms. systolic algorithms can be implemented in Occam as soft-systolic algorithms. With this knowledge, we developed AFO to automatically generate Occam programs from FP programs that have corresponding systolic algorithms, in the hope of generating parallel programs without needing to know the details of low-level communications, and thus greatly improving the productivity of parallel programming.

关键词： FP OCCAM PARALLEL PROGRAMMING PROGRAM TRANSLATION REGULAR ARRAY algorithms systolic algorithms TRANSPUTERS

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DESIGNING systolic algorithms USING SEQUENTIAL-MACHINES

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IEEE TRANSACTIONS ON COMPUTERS 1986年第6期35卷 531-542页

作者： IBARRA, OH KIM, SM PALIS, MA Department of Computer Science University Of Minnesota Minneapolis MN 5545

We present a tool that is useful in the design and analysis of systolic systems. Specifically, we give characterizations of systolic arrays in terms of (single processor) sequential machines which are easier to program and to analyze. We give several examples to illustrate the utility of the design tool. In particular, we show how systolic designs for such problems as integer bitwise multiplication, dynamic programming, and language recognition can easily be derived using the characterizations. We also present some new results concerning the properties and computational power of systolic arrays which can be obtained using the characterizations.

关键词： Characterizations VLSI design tool sequential machines systolic algorithms

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A study of systolic algorithms for VLSI processor arrays and optical computing

A study of systolic algorithms for VLSI processor arrays and...

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作者： K. G. Margaritis Loughborough University of Technology

学位级别：博士

This thesis presents some new. systolic algorithms for numerical computation, that are suitable for implementation on VLSI processor arrays or optical processors. Chapter 1 is an introduction to the environment for the development of the systolic approach, followed by an over- view of major research areas in systolic systems. Chapter 2 contains basic mathematical definitions and a brief intro- duction to specific areas of numerical analysis. Chapter 3 starts with some basic definitions and terminology for sys- tolic computing; then fundamental systolic algorithms are described. Following is a review of some transformation techniques and an introduction to systolic 'programming and soft-systolic simulation. Finally, systolic and optical com- puting are combined, and a framework for developing systolic algorithms is outlined. Chapter 4 investigates systolic algorithms for the solution of polynomial equations, and the systolic calcula- tion of the roots of the characteristic equation of certain matrices. Chapter 5 presents systolic algorithms for the efficient solution and the ·updating of the solution of linear systems of equations, using LU decomposition. Chapter 6 develops the concept of pipelining systolic a 7 r a y s ~ as well as the combination of area and time expan- Slon, 1n iterative solution of linear systems of equations, based on series of systolic matrix-vector multiplications. Chapter 7 further develops the idea of expanding iterative systolic algorithms in area and/or in time. The systolic implementation of successive matrix-matrix multiplications is discussed and then a group of algorithms based on matrix powering is studied. Chapter 8 presents some optical sys- tolic algorithms. The direct mapping of VLSI systolic algo- rithms on optical processors is discussed, and then, the Outer Product processor is used for the optical systolic implementation of basic matrix computations. Chapter 9 completes this thesis with some general con- clusions, and suggesti

关键词： parallel processing systolic algorithms VLSI processor arrays optical computing polynomial equations linear systems of equations matrix eigen-problem solution matrix functions

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Optimal systolic array algorithms for tensor product

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APPLIED MATHEMATICS AND COMPUTATION 2005年第1期168卷 496-518页

作者： Mishra, PK Birla Inst Technol Dept Appl Math Ranchi 835215 Bihar India

In this paper we examine the computational complexity of optimal systolic array algorithms for tensor product. We provide a time minimal schedule that meets the computed processor lower and upper bounds including one for tensor product. Our principle contribution is to find lower and upper bounds in the algorithm and its implementation for generating function and find processor-time-minimal schedule. (c) 2004 Elsevier Inc. All rights reserved.

关键词： computational complexity systolic algorithms tensor product lower and upper bounds

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algorithms and systolic Architectures for Multidimensional Adaptive Filtering Via McClellan Transformations

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1992年第1期2卷 60-71页

作者： Shapiro, Jerome M. Staelin, David H. MIT Lincoln Lab Lexington MA 02173 USA MIT Elect Res Lab Cambridge MA 02139 USA

algorithms an developed simultaneously with systolic architectures for multidimensional adaptive filtering. Because of the extremely high data rate required for real-time video processing, even with the use of highly concurrent algorithms and architectures, there is a strong motivation to limit the size of any adaptation problem. The combination of the McClellan transformation as an efficient parametrization for a multidimensional least-squares;(LS) adaptive filter, coupled with systolic arrays to adapt and Implement the filter, yields a novel solution to the problem of adapting a large zero-phase finite impulse response (FIR) multidimensional filter, having arbitrary directional biases, with only a few parameters. Furthermore, it is shown that these filters can be adapted abruptly on a block-by-block basis without causing blocking effects. After developing a basic processing element for a systolic array realization of the Chebychev structure for the McClellan transformation, It Is shown that for a given 2-D transformation function, the adaptation of the I-D prototype filter becomes a small multichannel adaptation problem similar to adaptive army problems. For real-time video applications, such an adaptation algorithm can be performed efficiently using a systolic array of CORDIC processing elements. A similar approach is also taken in developing algorithms to adapt the 2-D transformation function.

关键词： ARCHITECTURE systolic algorithms algorithms MULTIDIMENSIONAL IMPULSE RESPONSE block foundation PROBLEM SOLUTION adaptive filters Systole Filters transformation function

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VLSI architectures for block matching algorithms using systolic arrays

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1996年第1期6卷 67-73页

作者： Pan, SB Chae, SS Park, RH Department of Electronic Engineering Sogang University Seoul South Korea Signal Processing Lab Samsung Electronics Company Limited Suwon South Korea

In this paper, we investigate hardware implementation of block matching algorithms (BMA's) for motion estimation of moving sequences. Using systolic arrays, we propose VLSI architectures for the two-stage BMA and full search (FS) BMA. The two-stage BMA using integral projections reduces greatly. computational complexity with its performance comparable td that of the FS BMA. The proposed hardware architectures for the two-stage BMA and FS BMA are faster than the conventional hardware architectures with lower hardware complexity. Also, the proposed architecture of the first stage of the two-stage BMA is modeled in VHDL and simulated. Simulation results show the functional validity of the proposed architecture.

关键词： VLSI computational complexity digital signal processing chips image matching image sequences motion estimation systolic arrays video signal processing VHDL VLSI architectures block matching algorithms full search BMA hardware arc ARCHITECTURE systolic algorithms image matching image sequences digital signal processing chips complexity classes block matching Very large scale integration motion estimation Video signal processing very high density lipoproteins

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ON THE systolic IMPLEMENTATION OF ASSOCIATIVE MEMORY ARTIFICIAL NEURAL NETWORKS

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PARALLEL COMPUTING 1995年第5期21卷 825-840页

作者： MARGARITIS, KG Department of Informatics University of Macedonia 156 Egnatias Street 54621 Thessaloniki Greece

This paper describes the systolic implementation of a class of Artificial Neural Networks generally termed as Associative Memories. Such networks are the Discrete Autocorrelator or Discrete Hopfield, the Bi-directional Associative Memory, the Temporal Associative Memory, the Linear Associative Memory and the Novelty Filter. Further, problems such as different weight updating strategies, higher order correlation techniques and Fuzzy pattern encoding are discussed. The Re-Usable Matrix Vector and Matrix Multiplication systolic Arrays form the basis of the systolic implementation.

关键词： systolic algorithms ARTIFICIAL NEURAL NETWORKS ASSOCIATIVE MEMORIES

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A DISCRETE FOURIER-TRANSFORM USING SWITCHED CAPACITOR CIRCUITS IN systolic ARRAY ARCHITECTURE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 1990年第12期37卷 1578-1580页

作者： RAUT, R BHATTACHARYYA, BB FARUQUE, SM Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada

Basic SC building blocks are introduced and interconnection of these blocks in a systolic array architecture is shown to yield the desired DFT components. Simulation results using implementation on a workstation and S... 详细信息

关键词： Switched capacitor circuits ARCHITECTURE systolic algorithms Workstations Building construction Fourier Transform array structure

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A systolic ARRAY ARCHITECTURE FOR THE APPLEBAUM-HOWELLS ARRAY

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 1990年第8期38卷 1310-1313页

作者： UENO, M KAWABATA, K MOROOKA, T Toshiba Research and Development Center Kawasaki Japan

A systolic array architecture for the Applebaum-Howells array is derived. The problem to be solved is the elimination of the global signal feedback loop in the conventional Applebaum-Howells array processor. The procedure involved in deriving the architecture consists of two steps: orthogonalization of the input element signals and elimination of the feedback loop. In the first step, the input element signals are orthogonalized with regard to each other by using the Gram-Schmidt processor, placed ahead of the Applebaum-Howells processor. It is shown in the second step that the orthogonality in the Gram-Schmidt processor output signals can remove the global signal feedback loop and that the Applebaum-Howells array can be implemented effectively by using a systolic array with regular structure and local communication. Simulation results also show that the proposed processor features desirable characteristics for the radiation pattern with low sidelobe level common to the Applebaum-Howells array.

关键词： ARCHITECTURE systolic algorithms Feedback loop PROCESSOR Building construction Radiation patterns orthogonality signals array structure

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