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systolic ARRAY ARCHITECTURE FOR GABOR DECOMPOSITION

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1995年第4期5卷 355-359页

作者： IYENGAR, G PANCHANATHAN, S UNIV OTTAWA DEPT ELECT ENGNMULTIMEDIA COMMUN RES LABOTTAWAON K1N 6N5CANADA

In this brief, we propose a combined systolic array-content addressable memory architecture for real-time Gabor decomposition. We then present codec designs for Progressive Image Transmission using this architecture. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles, Gabor functions also achieve the lowest bound on the joint uncertainty of data, However these functions are not orthogonal and hence an analytic solution for the decomposition does not exist, Recently it has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of image data. For an n x n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM, Simulations and complexity studies show that this architecture can achieve real-time performance with current VLSI technology.

关键词： codecs Building construction ARCHITECTURE image data transformation matrix Image communication systems Data compression basis functions systolic algorithms Image compression array structure

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A reconfigurable bit-serial VLSI systolic array neuro-chip

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 1997年第1期44卷 53-70页

作者： Murtagh, PJ Tsoi, AC UNIV WOLLONGONG FAC INFORMAT WOLLONGONG NSW 2522 AUSTRALIA

A dynamically reconfigurable bit-serial systolic array implemented in 1.2-mu m double-metal P-well CMOS is described. This processor array is proposed as the central computational unit in the Reconfigurable systolic Array (RSA) neuro-computer and performance estimates suggest that a 64 IC system (containing a total of 1024 usable processors) can achieve a learning rate of 1134 MCUPS on the NETtalk problem, The architecture employs reconfiguration techniques for both fault-tolerance and functionality, and allows a number of neural network models (in both the recall and learning phases) from associative memory networks, supervised networks, and unsupervised networks to be supported, (C) 1997 Academic Press.

关键词： Networks Implementation ARRAY PROCESSORS systolic algorithms PROCESSOR learning rate configurability Network Fault tolerance p-well bit serial

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PRAGMATIC APPROACH TO systolic DESIGN

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1990年第4期137卷 277-282页

作者： MANOHAR, S BAUDET, G UNIV RHODE ISL DEPT COMP SCIKINGSTONRI 02881

Limitations of current systolic designs are pointed out and new constraints are imposed to make systolic solutions practical. Matrix multiplication is used as an illustration, and a simple but very high performance systolic architecture, the supercoprocessor for matrix problems (S-MP), which satisfies these constraints is presented. Implementation alternatives for the linear systolic array for matrix-vector multiplication, which forms the core of the S-MP, are also described.

关键词： systolic algorithms Constraint Systole Matrix multiplication ILLUSTRATIONS

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systolic KALMAN FILTERING - AN OVERVIEW

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IEE PROCEEDINGS-D CONTROL THEORY AND APPLICATIONS 1990年第4期137卷 235-244页

作者： GASTON, FMF IRWIN, GW Department of Electrical & Electronic Engineering Queen's University of Belfast Belfast UK

The paper reviews published systolic algorithms for both standard and square-root Kalman filtering. The formation of these complex arrays from simpler ones for matrix computations, including multiplication, backsubstitution, orthogonal decomposition and the Schur complement, is described. The Kalman filter arrays are compared in terms of the number of parallel computations required and the speed and efficiency of the algorithm.

关键词： parallel computations matrix computations Kalman filtering orthogonal decomposition multiplication backsubstitution parallel algorithms systolic algorithms Signal processing and detection Schur complement Information theory Kalman filters filter arrays Programming and algorithm theory filtering and prediction theory

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HIGH-SPEED SIGNAL-PROCESSING USING systolic ARRAYS OVER FINITE RINGS

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IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS 1988年第3期6卷 504-512页

作者： TAHERI, M JULLIEN, GA MILLER, WC Department of Electrical Engineering University of Windsor Windsor ONT Canada

A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3- mu m CMOS process.

关键词： systolic algorithms Finite residue number systems Fasting signal processing Very large scale integration Fields

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systolic ALGORITHM FOR POLYNOMIAL INTERPOLATION AND RELATED PROBLEMS

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PARALLEL COMPUTING 1991年第4-5期17卷 493-503页

作者： SCHRODER, H MURTHY, VK KRISHNAMURTHY, EV FUJITSU AUSTRALIA LTD SYDNEYAUSTRALIA AUSTRALIAN NATL UNIV RES SCH PHYS SCICOMP SCI LABCANBERRAACT 2601AUSTRALIA

This paper describes a systolic algorithm for interpolation and evaluation of polynomials over any field using a linear array of processors. The periods of these algorithms are O(n) for interpolatin and O(1) for evaluation. This algorithm is readily adapted for Chinese remaindering, easily generalized for the multivariable interpolation and can be extended for rational interpolation to produce Pade approximants. The instruction systolic array implementation of the algorithm is presented here.

关键词： CHINESE REMAINDERING EVALUATION INTERPOLATION POLYNOMIALS INSTRUCTION systolic ARRAYS LAGRANGE INTERPOLANT NEWTON INTERPOLATION PERIOD OF ALGORITHM QUORUM SECURITY LOCKS systolic algorithms systolic ARCHITECTURES

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systolic-based parallel architecture for the longest common subsequences problem

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INTEGRATION-THE VLSI JOURNAL 1998年第1期25卷 53-70页

作者： Luce, G Myoupo, JF Univ Picardie LaRIA Lab Rech Informat Amiens Fac Math & Informat F-80039 Amiens France

In this paper we design a new and efficient systolic architecture for the longest common subsequences problem which is, given two finite strings on any alphabet, to recover a subsequence of maximal length of both strings. A natural extension to this problem is to determine the set of all longest common subsequences of the two given strings. First, we present a modular linear time algorithm on an input/output bounded and fault-tolerant semi-mesh systolic structure for the longest common subsequence problem. Then, we extend this algorithm to the set of all longest common subsequences problem. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： systolic algorithms modularity fault tolerance dynamic programming longest common subsequences

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3-dimensional systolic architecture for parallel VLSI implementation of the discrete cosine transform

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1996年第5期143卷 255-258页

作者： Nayak, SS Meher, PK BERHAMPUR UNIV DEPT ELECT SCIBERHAMPUR 760007ORISSAINDIA

Two different linear systolic arrays have been suggested for the computation of discrete cosine transform (DCT). The proposed linear arrays are complementary to each other in the sense that the output of the linear arrays of one type may be fed as the input for the linear arrays of the other type. This feature of the proposed linear arrays has been utilised for designing a bilayer structure for computing the prime-factor DCT. It is interesting to note that the proposed structure does not require any hardware/time for transposition of the intermediate results. The desired transposition is achieved by orthogonal alignment of the linear arrays of the upper layer with respect to those of the lower layer. The proposed structures provide high throughput of computation due to fully pipelined processing, and massive parallelism employed in the bilayer architecture.

关键词： discrete cosine transform systolic algorithms signal processing VLSI

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systolic ARRAYS FOR VITERBI PROCESSING IN COMMUNICATION-SYSTEMS WITH A TIME-DISPERSIVE CHANNEL

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IEEE TRANSACTIONS ON COMMUNICATIONS 1988年第10期36卷 1148-1156页

作者： PROVENCE, JD GUPTA, SC Department of Electrical Engineering Southern Methodist University Dallas TX USA

The theory and design of systolic arrays for Viterbi processing in communication systems with a time-dispersive time-varying channel is discussed. The architecture, algorithms, and processor elements, for a two-dimensional systolic array are described. The array supports the branch metric computations required for an adaptive Viterbi processor. The array is designed so that computations propagate along the rows of the array, while data symbols propagate along the columns. All interprocessor data flow and connections within the array are nearest-neighbor. The array illustrates how the Viterbi-processor algorithms can be structured to achieve a high degree of computational concurrency. Variations in the array design are described and evaluated in terms of computational resource requirements and utilization and computational throughput. A high-bandwidth memory interface is proposed, and system design considerations are discussed.

关键词： arrays COMMUNICATION SYSTEMS systolic algorithms dispersive channels resource requirements

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STATISTICAL-ANALYSIS OF SIMULATION-GENERATED TIME-SERIES - systolic VS SEMI-systolic CORRELATION ON THE CONNECTION MACHINE

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PARALLEL COMPUTING 1992年第5期18卷 575-588页

作者： DONTJE, T LIPPERT, T PETKOV, N SCHILLING, K UNIV GESAMTHSCH WUPPERTAL FACHBEREICH PHYSGAUSSSTR 20W-5600 WUPPERTAL 1GERMANY THINKING MACHINES CORP CAMBRIDGEMA 02142

Autocorrelation becomes an increasingly important tool to verify improvements in the state of the simulational art in Lattice Gauge Theory. Semi-systolic and full-systolic algorithms are presented which are intensively used for correlation computations on the Connection Machine CM-2. The semi-systolic algorithm makes use of an intrinsic, microprogrammed global-add reduction function which is implemented extremely well on the Connection Machine. Nevertheless, the full-systolic correlation algorithm which makes use only of local communication and computation operations turns out to be substantially superior to the semi-systolic scheme whose basic step involves a non-local sum computation that extends over the entire machine.

关键词： systolic algorithms CORRELATION CONNECTION MACHINE GLOBAL ADDITION

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