A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented in this paper. It has very widely applications in DVB, HDtV and satellite commu...
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ISBN:
(纸本)0780379845
A concatenated decoder mainly composed of depunctured Viterbi decoder, convolutional deinterleaver, and Reed-Solomon decoder is presented in this paper. It has very widely applications in DVB, HDtV and satellite communication systems. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. the algorithms of Viterbi decoder and RS decoder are modified t-algorithrn and modified Euclidean algorithm, respectively. Furthermore, the finite field multipliers and inversion over composite fields was adapted to optimize area and power in RS decoder, which reduced the area near to 25% compared to the conventional finite fields. the proposed concatenated decoder has about 81,000 gates except RAM model, which implemented in 100MHz using 0.25um CMOS process.
turbo codes need to be used with reasonably long blocks of data which invariably lead to encoding delay (latency) and decoding delay of the order of O(N) due to the finite computational speed of the processor. Recentl...
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turbo codes need to be used with reasonably long blocks of data which invariably lead to encoding delay (latency) and decoding delay of the order of O(N) due to the finite computational speed of the processor. Recently it was shown that if the hardware complexity of W > 1 processors was acceptable, then the decoding delay could be reduced to O(N/W) without much performance degradation, by decoding the turbo code in a parallel fashion. In this letter we show thatthe decoding delay could be further reduced if the component decoders use parallel versions of soft outputt-algorithms instead of parallel versions of the MAP algorithm.
In this paper, we evaluate the bit error rate (BER) performance of a coordinate interleaved trellis coded QPSK with t-algorithm. We employ a coordinate interleaving which breaks up burst errors, caused by fading, more...
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In this paper, we evaluate the bit error rate (BER) performance of a coordinate interleaved trellis coded QPSK with t-algorithm. We employ a coordinate interleaving which breaks up burst errors, caused by fading, more effectively than symbol interleaving. We employ a rate-1/2 convolutional codes and the performance is evaluated on Rayleigh fading channels in terms of bit error rate (BER) by analysis and computer simulation. We consider using of the code which having a long effective code length (ECL). For this reason, we employ a decoder based on t-algorithm instead of Viterbi algorithmto avoid the complexity in the decoding. As the results, we achieve satisfactory BER performance with a slight computation in the decoding algorithm and the finite interleaving size.
A t-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network is proposed in order to achieve the balance of the computational load among the processors and atthe ...
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ISBN:
(纸本)0780318625
A t-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network is proposed in order to achieve the balance of the computational load among the processors and atthe same time to reduce the communication to a bare minimum. this algorithm is implemented on a network of workstations using the communication primitives send and receive on sockets. Finally, the tabulated results on the timings obtained on the ISCAS[8] benchmark circuits are presented.
this paper identifies the distributed simulation synchronization problem with a mathematical programming problem and examines synchronization algorithms from this standpoint.
this paper identifies the distributed simulation synchronization problem with a mathematical programming problem and examines synchronization algorithms from this standpoint.
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