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Coordinate interleaved trellis coded QPSK with t-algorithm on Rayleigh fading channel

IEICE tRANSACtIONS ON COMMUNICAtIONS 1996年第9期E79B卷 1248-1255页

作者： Nakamura, H Yamazato, t Katayama, M Ogawa, A NAGOYA UNIV SCH ENGN NAGOYA AICHI 46401 JAPAN

In this paper, we evaluate the bit error rate (BER) performance of a coordinate interleaved trellis coded QPSK with t-algorithm. We employ a coordinate interleaving which breaks up burst errors, caused by fading, more effectively than symbol interleaving. We employ a rate-1/2 convolutional codes and the performance is evaluated on Rayleigh fading channels in terms of bit error rate (BER) by analysis and computer simulation. We consider using of the code which having a long effective code length (ECL). For this reason, we employ a decoder based on t-algorithm instead of Viterbi algorithm to avoid the complexity in the decoding. As the results, we achieve satisfactory BER performance with a slight computation in the decoding algorithm and the finite interleaving size.

关键词： t-algorithm convolutional code coordinate interleaving fading channels

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High performance ACS for Viterbi decoder using pipeline t-algorithm

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ALEXANDRIA ENGINEERING JOURNAL 2015年第3期54卷 447-455页

作者： Vaithiyanathan, D. Nargis, J. Seshasayanan, R. Anna Univ Dept Elect & Commun Engn Chennai 600025 Tamil Nadu India Aalim Muhammed Salegh Coll Engn Dept Elect & Commun Engn Chennai Tamil Nadu India

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to the large number of trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add Compare Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of Viterbi decoder mainly depends on its efficient implementation of ACS module, in this paper, we propose a modified pipelined architecture for the ACS of Viterbi decoder. this is derived by employing the technique of re-timing;further the architecture is also reconfigured to support various wireless standards. the architecture has been implemented in Xilinx Vertex 6 FPGA device to make the comparison between our architecture and the existing architecture. From the analysis done on ACS implementation, it is found that the resource requirements, delay and power consumption are optimized significantly for the proposed architecture compared to existing pipelined architecture. the results obtained from the analysis show that frequency of the system is increased up to 165 MHz with reduced area. the cell level performance is also obtained using Cadence Encounter (R) tool with tSMC 180 nm CMOS technology. (c) 2015 Faculty of Engineering, Alexandria University. Production and hosting by Elsevier B.V.

关键词： Viterbi decoder t-algorithm Add Compare Select (ACS) Pipelining Field Programmable Gate Arrays (FPGAs)

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LOGIC SIMULAtION USING t-algorithm ON NEtWORK OF WORKStAtIONS

LOGIC SIMULATION USING T-ALGORITHM ON NETWORK OF WORKSTATION...

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1994 Annual International Conference of the IEEE Region-10 - Frontiers of Computer technology

作者： SUNDARAM, S SRINIVAS, MK INDIAN INST SCI CTR SUPERCOMP EDUC & RESCOMP AIDED DESIGN LABBANGALORE 560012KARNATAKAINDIA

ISBN: (纸本)0780318625

A t-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network is proposed in order to achieve the balance of the computational load among the processors and at the same time to reduce the communication to a bare minimum. this algorithm is implemented on a network of workstations using the communication primitives send and receive on sockets. Finally, the tabulated results on the timings obtained on the ISCAS[8] benchmark circuits are presented.

关键词： LOGIC SIMULAtION DIStRIBUtED PROCESSING NEtWORK OF WORKStAtIONS t-algorithm

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AN EFFICIENt ARCHItECtURE OF tRANSPARENt-SCAN SEQUENCES AMONG LOGIC BLOCKS USING t-algorithm 2

AN EFFICIENT ARCHITECTURE OF TRANSPARENT-SCAN SEQUENCES AMON...

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2nd International Conference on Electronics and Communication Systems (ICECS)

作者： Rubini, D. Esther, t. NPRCET Dindigul Tamil Nadu India

ISBN: (纸本)9781479972258

An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. the conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage. In order to overcome above problems a new technique called t-algorithm is proposed. this algorithm reduces the clocking in a circuit and optimizes the testing architecture. the testing architecture consists of Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) blocks. the optimization process is mainly focused on the reduction of clock levels, instead of applying clock pulse to each flip-flop separately, the output taken from the MUX is applied to next flip-flops.

关键词： transparent-scan launch-off-capture launch-off-shift t-algorithm

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Parallel decoding of turbo codes using soft output t-algorithms

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IEEE COMMUNICAtIONS LEttERS 2001年第8期5卷 352-354页

作者： Dasgupta, U Narayanan, KR Texas Instruments Inc DSPS R&D Ctr Dallas TX 75206 USA Texas A&M Univ Dept Elect Engn College Stn TX 77843 USA

turbo codes need to be used with reasonably long blocks of data which invariably lead to encoding delay (latency) and decoding delay of the order of O(N) due to the finite computational speed of the processor. Recently it was shown that if the hardware complexity of W > 1 processors was acceptable, then the decoding delay could be reduced to O(N/W) without much performance degradation, by decoding the turbo code in a parallel fashion. In this letter we show that the decoding delay could be further reduced if the component decoders use parallel versions of soft output t-algorithms instead of parallel versions of the MAP algorithm.

关键词： decoding delay iterative soft output decoding MAP-based decoding parallel decoding scheme t-algorithm

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Low-power state-parallel relaxed adaptive Viterbi decoder

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IEEE tRANSACtIONS ON CIRCUItS AND SYStEMS I-REGULAR PAPERS 2007年第5期54卷 1060-1068页

作者： Sun, Fei Zhang, tong Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA

Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. this limitation also incurs power and silicon area overhead. this paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput.

关键词： adaptive Viterbi algorithm low power t-algorithm very large-scale integration (VLSI) architecture

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An approach for adaptively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes

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IEEE tRANSACtIONS ON SIGNAL PROCESSING 2004年第5期52卷 1443-1451页

作者： Henning, R Chakrabarti, C Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

Significant power reduction can be achieved by exploiting real-time variation in system characteristics. An approach is proposed and studied herein that exploits variation in signal transmission system characteristics to reduce power consumption while decoding convolutional codes. With this approach, Viterbi decoding is adaptively approximated by varying the pruning threshold of the t-algorithm and truncation length while employing trace-back memory management. A heuristic is given for finding and adaptively applying pairs of pruning threshold and truncation length values that significantly reduce power to variations in signal-to-noise ratio (SNR), code rate, and maximum acceptable bit-error rate (BER). the power reduction potential of different levels of adaptation is studied. High-level energy reduction estimates of 80% to 97% compared with Viterbi decoding are shown. Implementation insight and general conclusions about when applications can particularly benefit from this approach are given.

关键词： convolutional code low power t-algorithm Viterbi algorithm

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An Efficient 4-D 8PSK tCM Decoder Architecture

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IEEE tRANSACtIONS ON VERY LARGE SCALE INtEGRAtION (VLSI) SYStEMS 2010年第5期18卷 808-817页

作者： He, Jinjin Wang, Zhongfeng Liu, Huping Oregon State Univ Sch Elect Engn & Comp Sci Corvallis OR 97331 USA Broadcom Corp Irvine CA 92617 USA

this paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (tCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. this scheme significantly reduces the required computation without degrading the performance. then, a new hybrid t-algorithm for a Viterbi decoder is developed by applying a t-algorithm on both branch metrics (BMs) and path metrics (PMs). tCM encoders usually employ high-rate convolutional codes that yield many more transition paths per state than low-rate codes do. this makes it feasible to purge unnecessary additions by applying the t-algorithm on BMs. Applying the t-algorithm on BMs instead of PMs allows one to move the "search-for-the-optimal" operation out of the add-compare-select-unit (ACSU) loop. Hence, the clock speed will not be affected. In addition, by combining the t-algorithm on BMs and the t-algorithm on PMs, the hybrid t-algorithm can reduce the computations required with the conventional t-algorithm on PMs by as much as 50%.

关键词： Add-compare-select unit (ACSU) t-algorithm trellis-coded modulation (tCM) Viterbi decoder (VD) VLSI

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Sequence error probability lower bounds for joint detection and estimation

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IEEE tRANSACtIONS ON COMMUNICAtIONS 2003年第3期51卷 347-351页

作者： Anastasopoulos, A Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

A commonly used lower bound on the probability of error of joint detection and estimation (JDE) algorithms is derived under the assumption that estimation is performed using the transmitted sequence, in a genie-aided fashion. Although it seems reasonable that this genie-aided receiver performs better than the original receiver, a proof of this fact is not available in the literature. In this letter, the validity of this bound is established for a general class of JDE algorithms, as well as for an important special case when the maximum-likelihood sequence detection criterion is used. the results are then extended to a well-known suboptimal JDE algorithm, namely, the t-algorithm. It is shown, however, that the technique used to prove this bound is not sufficient for establishing the validity of the bound for the M-algorithm and the per-survivor processing algorithm.

关键词： correct decision feedback generalized-likelihood ratio test joint detection estimation lower bounds M-algorithm per-survivor processing sequence error probability t-algorithm

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Parallel high-throughput limited search trellis decoder VLSI design

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IEEE tRANSACtIONS ON VERY LARGE SCALE INtEGRAtION (VLSI) SYStEMS 2005年第9期13卷 1013-1022页

作者： Sun, F Zhang, t Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA

Limited search trellis decoding algorithms have great potentials of realizing low power due to their largely reduced computational complexity compared with the widely used Viterbi algorithm. However, because of the lack of operational parallelism and regularity in their original formulations, the limited search decoding algorithms have been traditionally ruled out for applications demanding very high throughput. We believe that, through appropriate algorithm and hardware architecture co-design, certain limited search trellis decoding algorithms can become serious competitors to the Viterbi algorithm for high-throughout applications. Focusing on the well-known t-algorithm, this paper presents techniques at the algorithm and VLSI architecture levels to design fully parallel t-algorithm limited search trellis decoders. We first develop a modified t-algorithm, called SPEC-t, to improve the algorithmic parallelism. then, based on the conventional state-parallel register exchange Viterbi decoder, we develop a parallel SPEC-t decoder architecture that can effectively transform, the reduced computational complexity at the algorithm level to the reduced switching activities in the hardware. We demonstrate the effectiveness of the SPEC-t design solution in the context of convolutional code decoding. Compared with state-parallel register exchange Viterbi decoders, the SPEC-t convolutional code decoders can achieve almost the same throughput and decoding performance, while realizing up to 56% power savings. For the first time, this work provides an approach to exploit the low power potential of the t-algorithm in very high throughput applications.

关键词： limited search trellis decoder low power parallel architecture SPEC-t t-algorithm Viterbi algorithm (VA) VLSI

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