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Virtualization Technology for tcp/ip offload engine

IEEE TRANSACTIONS ON CLOUD COMPUTING 2014年第2期2卷 117-129页

作者： Chang, En-Hao Wang, Chen-Chieh Liu, Chien-Te Chen, Kuan-Chung Chen, Chung-Ho Natl Cheng Kung Univ Inst Comp & Commun Engn Dept Elect Engn Tainan 701 Taiwan Ind Technol Res Inst Informat & Commun Res Lab Hsinchu 31040 Taiwan

Network I/O virtualization plays an important role in cloud computing. This paper addresses the system-wide virtualization issues of tcp/ip offload engine (TOE) and presents the architectural designs. We identify three critical factors that affect the performance of a TOE: I/O virtualization architectures, quality of service (QoS), and virtual machine monitor(VMM) scheduler. In our device emulation based TOE, the VMM manages the socket connections in the TOE directly and thus can eliminate packet copy and demultiplexing overheads as appeared in the virtualization of a layer 2 network card. To further reduce hypervisor intervention, the direct I/O access architecture provides the per VM-based physical control interface that helps removing most of the VMM interventions. The direct I/O access architecture out-performs the device emulation architecture as large as 30 percent, or achieves 80 percent of the native 10 Gbit/s TOE system. To continue serving the TOE commands for a VM, no matter the VM is idle or switched out by the VMM, we decouple the TOE I/O command dispatcher from the VMM scheduler. We found that a VMM scheduler with preemptive I/O scheduling and a programmable I/O command dispatcher with deficit weighted round robin(DWRR) policy are able to ensure service fairness and at the same time maximize the TOE utilization.

关键词： Hypervisor I/O virtualization tcp/ip offload engine VMM scheduler

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Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA

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SENSORS 2023年第10期23卷 4690-4690页

作者： Yang, Dan Xu, Xuhan Chen, Tianyang Chen, Yanhao Zhang, Junjie Shanghai Univ Shanghai Inst Adv Commun & Data Sci Key Lab Specialty Fiber Opt & Opt Access Networks Shanghai 200072 Peoples R China

The tcp protocol is a connection-oriented and reliable transport layer communication protocol which is widely used in network communication. With the rapid development and popular application of data center networks, high-throughput, low-latency, and multi-session network data processing has become an immediate need for network devices. If only a traditional software protocol stack is used for processing, it will occupy a large amount of CPU resources and affect network performance. To address the above issues, this paper proposes a double-queue storage structure for a 10G tcp/ip hardware offload engine based on FPGA. Furthermore, a TOE reception transmission delay theoretical analysis model for interaction with the application layer is proposed, so that the TOE can dynamically select the transmission channel based on the interaction results. After board-level verification, the TOE supports 1024 tcp sessions with a reception rate of 9.5 Gbps and a minimum transmission latency of 600 ns. When the tcp packet payload length is 1024 bytes, the latency performance of TOE's double-queue storage structure improves by at least 55.3% compared to other hardware implementation approaches. When compared with software implementation approaches, the latency performance of TOE is only 3.2% of the software approaches.

关键词： FPGA tcp/ip offload engine network traffic low latency model analysis

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Implementation of a Software-Based tcp/ip offload engine Using Standalone tcp/ip without an Embedded OS

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JOURNAL OF INFORMATION SCIENCE AND engineERING 2011年第6期27卷 1871-1883页

作者： Yoon, In-Su Chung, Sang-Hwa Kwon, Yoon-Geun Pusan Natl Univ Dept Comp Engn Pusan 609735 South Korea

A number of tcp/ip offload engines have been developed to reduce the CPU load of processing tcp/ip, but most of them are implemented in hardware. Although hardware-based TOEs have a high performance, they lack the flexibility to accept changes in the tcp/ip. To preserve flexibility, we implemented a software-based TOE, called HL-tcp 100134 (High-performance Lightweight tcp/ip). The HL-tcp is a standalone tcp/ip without an embedded OS. The TOE using the HL-tcp has features of a zero-copy sending mechanism and an efficient DMA mechanism for tcp retransmission. It also fully utilizes offload features in the Ethernet. Our experimental results show that the TOE using the HL-tcp can achieve a bandwidth of 453 Mbps with almost zero CPU utilization, compared with a general gigabit Ethernet, which has a CPU utilization of approximately 23%.

关键词： tcp/ip offload engine TOE tcp/ip gigabit Ethernet embedded systems

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40Gbps Multi-Connection tcp/ip offload engine

40Gbps Multi-Connection TCP/IP Offload Engine

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2011年无线通信与信号处理国际会议(WCSP 2011)

作者： Yong Ji Qing-Sheng Hu Institute of RF- & OE-Ics Southeast UniversityNanjing China Institute of RF- & OE-ICs Southeast University Nanjing China

tcp/ip stack is the workhorse protocol of the Internet. The processing of the tcp/ip over Ethernet is traditionally accomplished by software running on the central processor, CPU or microprocessor. As the speed of Ethernet grows from 10Mbits/s to 10Gbits/s, the CPU can’t afford the large amount of tcp/ip protocol processing required. So the tcp/ip protocol processor becomes an efficient and a must method to offload CPU burdens. This paper proposes a tcp/ip Internet protocol processing system architecture, which is to implement transport layer, network layer and data link layer, and support configurable number of connections. The design is implemented on Altera StratixIV FPGA. The performance estimation shows that our system can provide high-speed tcp/ip transmission rate up to 4Gbps as receiver and 40Gbps as sender.

关键词： tcp/ip offload engine FPGA Multi connections

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Design of a Lightweight tcp/ip Protocol Stack with an Event-Driven Scheduler

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JOURNAL OF INFORMATION SCIENCE AND engineERING 2012年第6期28卷 1059-1071页

作者： Jang, Joonhyouk Jung, Jinman Cho, Yookun Choi, Sanghoon Shin, Sung Y. Seoul Natl Univ Sch Comp Sci & Engn Seoul 151744 South Korea Soongsil Univ Sch Comp Seoul 156743 South Korea S Dakota State Univ Elect Engn & Comp Sci Dept Brookings SD 57007 USA

The traditional tcp/ip protocol stack is associated with shortcomings related to the context-switching overhead and redundant data copying. The software-based TOE (tcp/ip offload engine), also known as lightweight tcp/ip, was developed to optimize the tcp/ip protocol stack to run on an embedded system. In this paper, we propose the design of a lightweight tcp/ip protocol stack that runs on an event-driven scheduler. An event-driven scheduler is one of the main components of a real-time operating system that provides essential functionalities for an embedded system in network communication. We discuss the problems involved in designing a lightweight tcp/ip with an event-driven scheduler, especially for the issues of tcp transmission and tcp retransmission. We implemented and evaluated the proposed tcp/ip stack on an embedded networking device and verified that the proposed tcp/ip stack is well suited for high-performance networking in embedded systems.

关键词： tcp/ip tcp/ip offload engine embedded system

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Design and implementation of a protocol offload engine for tcp/ip and remote direct memory access based on hardware/software coprocessing

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MICROPROCESSORS AND MICROSYSTEMS 2009年第5-6期33卷 333-342页

作者： Jang, Hankook Chung, Sang-Hwa Yoo, Dae-Hyun Pusan Natl Univ Dept Comp Engn Pusan 609735 South Korea

This paper presents the design and implementation of a protocol offload engine that processes tcp/ip and remote direct memory access (RDMA) protocols by means of hardware/software coprocessing. In the offload engine, time-consuming operations such as tcp/ip header generation are implemented as hardware to improve performance. The software performs control operations and RDMA header generation. In the experiments and analyses, it is proved that the hardware can provide satisfactory performance to process all operations at speeds of over 1 Gbps. Our engine can offload most protocol processing overheads - up to 95% to 100% - from the host CPU. Finally, although the embedded processors operate with a 300 MHz clock that is seven times slower than the clock of the host CPU, our engine shows maximum bandwidths of 673 Mbps for tcp/ip and 551 Mbps for RDMA on a gigabit Ethernet network. (C) 2009 Elsevier B.V. All rights reserved.

关键词： Embedded system Hardware/software coprocessing Protocol offloading tcp/ip offload engine Remote direct memory access

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Desenvolvimento de uma arquitetura parametrizável para processamento da pilha tcp/ip em hardware

Desenvolvimento de uma arquitetura parametrizável para proc...

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作者： Hamerski, Jean Carlo

The advent of new transmission lines stimulates an explosive increase of the Internet data-transmission rate. Thus, the tcp/ip processing based on software became a bottleneck, because it cannot reach the transmission line speed required, specially in the transmission of transport layer packets. This limitation brings the necessity of implementation of the tcp/ip processing in hardware, what it would bring advantages in the acceleration of data flow processing. In this way, this work presents the iNetCore architecture, described in VHDL, able to process the transport and network layers protocols in hardware. Two implementations of this architecture were implemented. The objective is to explore the design space and to analyze the results in ASIC and FPGA technology synthesis. Also, a simulation environment was built to analyze the performance in the packets computation. A HW/SW architecture containing the iNetcore was prototyped on Virtex-II Pro Development System board. In conjunction with this architecture, it was implemented a communication interface with OPB bus, which makes possible the development of application layer softwares that may use the hardware tcp/ip stack developed. Finally, experiments were realized in order to evaluate the HW/SW architecture performance in the tcp segments processing. The HW/SW architecture together with the iNetCore reached a throughput of about 1.45 Gbps in the tcp/ip packets processing. It proves its potential to use available bandwidth in gigabit networks. ...

关键词： Microeletrônica tcp/ip offload engine Throughput tcp/ip performance Dissertação

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Gigabit networking: Linux kernel module suite with support for TOE and GNIC

Gigabit networking: Linux kernel module suite with support f...

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5th IASTED International Conference on Communications, Internet, and Information Technology

作者： Kushwaha, Neeraj Oh, Soo-Cheol Kim, Sun-Wook Kim, Seong-Woon Elect & Telecommun Res Inst Taejon 305606 South Korea

ISBN: (纸本)9780889866133

The current de facto standard for inter networking is the tcp/ip protocol suite to transmit data over Local Area Networks (LANs), Wide Area Networks (WANs) and the Internet. As network speed rises to Gigabit Ethernet and 10 Gigabit Ethernet, host CPU can become severe bottleneck in high speed computing as tcp/ip processing places a heavy burden on host CPU. It has been known that CPU horsepower in today's server is just sufficient enough to handle tcp/ip processing, leaving no CPU cycles for critical business applications. Recently tcp/ip offload engine (TOE) technology, which processes tcp/ip on a network adapter instead of host CPU, has become an important approach to this problem. In this paper, we present Linux kernel module suite with dual support for TOE and general NIC. Limix. kernel module suite is a 2-tier design architecture having TOE Switch Module (TSM) and TOE Protocol Module (TPM). The TOE adapter along with TOE based Linux kernel module suite offloads the processing of tcp/ip protocol from host & enhances the network data transmission i.e. increases the throughput and lowers client response time. Experimental results also show that the TOE Linux kernel module suite imposes fewer loads on the host CPU.

关键词： Gigabit Networking Operating System support tcp/ip offload engine Linux Kernel Module

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