This paper proposes a sparse check matrix H generation method and a regular AA-LDPC (architecture-aware low-density parity-check) code decoder architecture. The generated H matrix is suitable for regular LDPC codes, a...
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ISBN:
(纸本)9781728192581
This paper proposes a sparse check matrix H generation method and a regular AA-LDPC (architecture-aware low-density parity-check) code decoder architecture. The generated H matrix is suitable for regular LDPC codes, avoiding the appearance of four-line loops. The decoder uses tdmp (turbo-decoding message-passing) and Log-Map algorithms, which can achieve faster convergence speed and higher throughput compared with traditional decoding algorithms. Use the scoreboard algorithm to solve the problem of data conflict between tdmp algorithm initialization and the first iteration. Extrinsic messages and posterior messages are stored in 6bit and 8bit respectively, the memory usage is reduced by more than 60% compared with the traditional method, and the chip area is reduced. The decoder module is written in high-level Chisel language, which effectively improves the development efficiency compared with verilog. Uvm (Universal Verification Methodology) was used to randomly generate 10,000 stimuli to verify the verilog code generated by Chisel. With a clock frequency of 290MHz, this architecture can decode any regular AA-LDPC(3, 27) code with a code rate of 8/9 9216-bit, with ten iterations and a data throughput rate of 450Mbps.
This paper presents a cost-effective scalable quasi-cyclic LDPC (QC-LDPC) decoder architecture for non-volatile memory systems (NVMS). A re-arranged architecture is proposed to eliminate the first-in-first-out (FIFO) ...
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ISBN:
(纸本)9781479903566
This paper presents a cost-effective scalable quasi-cyclic LDPC (QC-LDPC) decoder architecture for non-volatile memory systems (NVMS). A re-arranged architecture is proposed to eliminate the first-in-first-out (FIFO) memory in conventional decoders, where the FIFO size is linearly proportional to the codeword size. The area reduction is 18.5% compared to the conventional decoder architecture. The scalable datapaths of the proposed decoder reduce the re-design cost and enable the flexibility of using QC-LDPC codes for NVMS. A prototyping decoder with maximum codeword size of 9280 bits is implemented in TSMC 90nm CMOS technology, and the core area is only 2.52mm(2) at 138.8MHz.
This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (tdmp) algorithm, this ...
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ISBN:
(纸本)9781457716171
This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (tdmp) algorithm, this architecture costs 8 similar to 16 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5x higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.
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