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IRIS Reimagined: Advancements in Intelligent Runtime System for task-based programming 1

2nd International Workshop on Asynchronous Many-task Systems and Applications (WAMTA)

作者： Miniskar, Narasinga Rao Lee, Seyong Beau, Johnston Young, Aaron Monil, Mohammad Alaul Haque Valero-Lara, Pedro Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (数字)9783031617638

ISBN: (纸本)9783031617621;9783031617638

task-based programming models are gaining traction in scientific computing. IRIS is a portable runtime system that exploits multiple heterogeneous programming systems and can discover available resources and manage multiple diverse programming systems (e.g., CUDA, Hexagon, HIP, Level Zero, OpenCL, and OpenMP) simultaneously. It accounts for the constraints of task dependencies and provides customizable scheduling policies to map those tasks to heterogeneous devices. In this paper, we present new capabilities added to IRIS to improve its portability for heterogeneous programming, build-friendliness, and performance efficiency. The new additions include vendor-specific kernel support, a runtime system with a foreign function interface to eliminate writing wrapper or boilerplate code for heterogeneous kernels, an easy-to-use and configurable CMake-based build environment, automatic and efficient data transfers and orchestration, and the Hunter and DAGGER toolchains to evaluate IRIS's task scheduling algorithms.

关键词： Heterogeneous Computing Runtime System IRIS DMEM CUDA HIP task based programming

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MatRIS: Addressing the Challenges for Portability and Heterogeneity Using tasking for Matrix Decomposition (Cholesky) 1

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2nd International Workshop on Asynchronous Many-task Systems and Applications (WAMTA)

作者： Monil, Mohammad Alaul Haque Miniskar, Narasinga Rao Valero-Lara, Pedro Teranishi, Keita Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (数字)9783031617638

ISBN: (纸本)9783031617621;9783031617638

The ubiquitous in-node heterogeneity of HPC and cloud computing platforms makes software portability and performance optimization extremely challenging. Described here, the MatRIS multilevel math library abstraction framework employs tasking to alleviate these difficulties. MatRIS includes the IRIS task-based runtime on the bottom level and exposes different layers of abstraction to render algorithms architecturally agnostic. MatRIS ensures the decomposition and creation of tasks that represent the necessary encapsulation of the optimized kernels from both vendor and open-source math libraries. Once built, MatRIS can select different combinations of accelerators at runtime, making it portable even on diverse heterogeneous architectures. By leveraging the IRIS runtime's features for managing heterogeneity, MatRIS deploys algorithms that remove the need to specify orchestration and data transfer. This study describes how the serial task abstraction of a tiled Cholesky factorization is made portable and scalable in the case of multi-device and multi-vendor heterogeneity on a node with NVIDIA and AMD GPUs by using MatRIS. First, we demonstrate that Cholesky in MatRIS provides multi-GPU scalability that offers competitive performance versus cuSolverMG. Then, we present the challenges and opportunities for heterogeneous execution.

关键词： Math Library Runtime System POTRF Cholesky Decomposition Portability Heterogeneity task based programming

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Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware 16

Tail-PASS: Resource-based Cache Management for Tiled Graphic...

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16th IEEE ISPA / 17th IEEE IUCC / 8th IEEE BDCloud / 11th IEEE SocialCom / 8th IEEE SustainCom

作者： Ceballos, German Hagersten, Erik Black-Schaffer, David Uppsala Univ Dept Informat Technol Uppsala Sweden

ISBN: (纸本)9781728111414

Modern graphics rendering is a very expensive process and can account for 60% of the battery consumption on current games. Much of the cost comes from the high memory bandwidth of rendering complex graphics. To render a frame, multiple smaller rendering passes called scenes are executed, with each one tiled for parallel execution. The data for each scene comes from hundreds of software resources (textures). We observe that each frame can consume up to 1000s of MB of data, but that over 75% of the graphics memory accesses are to the top-10 resources, and that bypassing the remaining infrequently accessed (tail) resources reduces cache pollution. Bypassing the tail can save up to 35% of the main memory traffic over resource-oblivious replacement policies and cache management techniques. In this paper, we propose Tail-PASS, a cache management technique that detects the most accessed resources at run-time, learns if it is worth bypassing the least accessed ones, and then dynamically enables/disables bypassing to reduce cache pollution on a per-scene basis. Overall, we see an average reduction in bandwidth-per-frame of 22% (up to 46%) by bypassing all but the top-10 resources and an 11% (up to 44%) reduction if only the top-2 resources are cached.

关键词： Cache bypassing Cache management Data placement Graphics rendering Rendering (computer graphics) task based programming

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taskUniVerse: A task-based Unified Interface for Versatile Parallel Execution 12th

TaskUniVerse: A Task-Based Unified Interface for Versatile P...

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12th International Conference on Parallel Processing and Applied Mathematics (PPAM)

作者： Zafari, Afshin Uppsala Univ Div Comp Sci Dept Informat Technol Lagerhyddsvagen 2 S-75237 Uppsala Sweden

ISBN: (纸本)9783319780245;9783319780238

task based parallel programming has shown competitive outcomes in many aspects of parallel programming such as efficiency, performance, productivity and scalability. Different approaches are used by different software development frameworks to provide these outcomes to the programmer, while making the underlying hardware architecture transparent to her. However, since programs are not portable between these frameworks, using one framework or the other is still a vital decision by the programmer whose concerns are expandability, adaptivity, maintainability and interoperability of the programs. In this work, we propose a unified programming interface that a programmer can use for working with different task based parallel frameworks transparently. In this approach we abstract the common concepts of task based parallel programming and provide them to the programmer in a single programming interface uniformly for all frameworks. We have tested the interface by running programs which implement matrix operations within frameworks that are optimized for shared and distributed memory architectures and accelerators, while the cooperation between frameworks is configured externally with no need to modify the programs. Further possible extensions of the interface and future potential research are also described.

关键词： High Performance Computing task based programming Parallel programming Unified interface

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Semi-Static and Dynamic Load Balancing for Asynchronous Hurricane Storm Surge Simulations

Semi-Static and Dynamic Load Balancing for Asynchronous Hurr...

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IEEE/ACM Parallel Applications Workshop - Alternatives To MPI (PAW-ATM)

作者： Bremer, Maximilian H. Bachan, John D. Chan, Cy P. Univ Texas Austin Inst Computat Engn & Sci Austin TX 78712 USA Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA 94720 USA

ISBN: (纸本)9781728102245

The performance of hurricane storm surge simulations is critical to forecast and mitigate the deadly effects of hurricane landfall. Supercomputers play a key role to run these simulations quickly;however, disruptive changes in future computer architectures will require adapting simulators to maintain high performance, such as increasing asynchrony and improving load balance. We introduce two new multi-constraint, fully asynchronous load balancers and a new discrete-event simulator (DGSim) that is able to natively model the execution of task-based hurricane simulations based on efficient one-sided, active message-based communication protocols. We calibrate and validate DGSim, use it to compare the algorithms' load balancing capabilities and task migration costs under many parameterizations, saving of over 5,000x core-hours compared to running the application code directly. Our load balancing algorithms achieve a performance improvement of up to 56 percent over the original static balancer and up to 97 percent of the optimal speed-up.

关键词： Asynchronous execution Discontinuous Galerkin Load balancing and task assignment Performance modeling Shallow water equations task based programming

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A task-based Algorithm for Reordering the Eigenvalues of a Matrix in Real Schur Form 12th

A Task-Based Algorithm for Reordering the Eigenvalues of a M...

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12th International Conference on Parallel Processing and Applied Mathematics (PPAM)

作者： Myllykoski, Mirko Umea Univ Dept Comp Sci S-90187 Umea Sweden

ISBN: (纸本)9783319780245;9783319780238

A task-based parallel algorithm for reordering the eigenvalues of a matrix in real Schur form is presented. The algorithm is realized on top of the StarPU runtime system. Only the aspects which are relevant for shared memory machines are discussed here, but the implementation can be configured to run on distributed memory machines as well. Various techniques to reduce the overhead and the core idle time are discussed. Computational experiments indicate that the new algorithm is between 1.5 and 6.6 times faster than a state of the art MPI-based implementation found in ScaLAPACK. With medium to large matrices, strong scaling efficiencies above 60% up to 28 CPU cores are reported. The overhead and the core idle time are shown to be negligible with the exception of the smallest matrices and highest core counts.

关键词： Eigenvalue reordering problem task based programming Shared memory machines

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Challenges of Reducing Cycle-accurate Simulation Time for TBP Applications

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Procedia Computer Science 2013年 18卷 1814-1823页

作者： Alexandru C. Iordan Magnus Jahre Lasse Natvig Norwegian University of Science and Technology Trondheim Norway

Cycle-accurate simulation is an important tool that depends on the computational power of supercomputers. Unfortunately, simulations of modern multi-core platforms can take weeks or months. In this paper, we look into the challenges of employing a sampling based technique for reducing simulation time of multi-threaded applications. We introduce FASTA, a simple 3- phase methodology for reducing the simulation time of task based Parallel (TBP) applications. FASTA takes advantage of the periodic behavior of parallel applications and identifies a small number of representative execution samples. By exploring a large design space we show that even though we can not use FASTA for every type of application, there are some for which a 12x speedup can be achieved with an accuracy error as low as 2.6%.

关键词： task based programming simulation chip-multiprocessor.

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