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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int Symposium on Cyberspace Safety and Security

作者： Boillot, Lionel Bosilca, George Agullo, Emmanuel Calandra, Henri INRIA Bordeaux Sud Ouest Mag Project Team 3D Ave UnivBP 1155 F-64013 Pau France Univ Tennessee Dept EECS ICL Knoxville TN 37996 USA INRIA Bordeaux Sud Ouest HiePACS Project Team F-33405 Talence France TOTAL EP Depth Imaging & High Performance Comp Houston TX 77057 USA

ISBN: (纸本)9781479961238

The level of hardware complexity of current super-computers is forcing the High Performance Computing (HPC) community to reconsider parallel programming paradigms and standards. The high-level of hardware abstraction provided by task-based paradigms make them excellent candidates for writing portable codes that can consistently deliver high performance across a wide range of platforms. While this paradigm has proved efficient for achieving such goals for dense and sparse linear solvers, it is yet to be demonstrated that industrial parallel codes-relying on the classical Message Passing Interface (MPI) standard and that accumulate dozens of years of expertise (and countless lines of code)-may be revisited to turn them into efficient task-based programs. In this paper, we study the applicability of task-based programming in the case of a Reverse Time Migration (RTM) application for Seismic Imaging. The initial MPI-based application is turned into a task-based code executed on top of the PaRSEC runtime system. Preliminary results show that the approach is competitive with (and even potentially superior to) the original MPI code on a homogeneous multicore node, and can more efficiently exploit complex hardware such as a cache coherent Non Uniform Memory Access (ccNUMA) node or an Intel Xeon Phi accelerator.

关键词： Intel Xeon Phi co-processors ccNUMA nodes elastic wave propagation runtime system task-based programming seismic methods Codes hardware abstraction message passing Earthquakes wave propagation preliminary data programming High Performance Computing mannose phosphate isomerase remote procedure calls

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Trade-Off of Offloading to FPGA in OpenMP task-based programming 14th

Trade-Off of Offloading to FPGA in OpenMP Task-Based Program...

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14th International Workshop on Open MP (IWOMP)

作者： Watanabe, Yutaka Lee, Jinpil Boku, Taisuke Sato, Mitsuhisa Univ Tsukuba Grad Sch Syst & Informat Engn Tsukuba Ibaraki Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan Univ Tsukuba Ctr Computat Sci Tsukuba Ibaraki Japan

ISBN: (纸本)9783319985213;9783319985206

In High-Performance Computing (HPC), Field Programmable Gate Array (FPGA) is attracting increased attention as an accelerator because its performance has been dramatically improved in recent years. On the other hand, task-based programming recently supported in OpenMP 4.0 enables to expose much parallelism by executing several tasks of the program in the form of a task graph. To accelerate the task-based parallel program by FPGA, it is useful for some dominant tasks frequently executed in parallel to be offloaded to FPGA as an asynchronous FPGA task. We present a performance optimization based on the trade-off between the kernel size and the number of asynchronously executed kernels in parallel in OpenMP task-based programming with FPGA tasks to make use of FPGA hardware resources efficiently. Since a "program" for FPGA is directly converted into the hardware, the hardware resource limitation raises a new issue in optimization on which and how to offload a task to FPGA. Taking task-based block Cholesky factorization as a motivating example, we present the trade-off on how to offload dominant "GEMM" task frequently executed in parallel in the execution of the task-graph. We found that under the limitation of the hardware resource, multiple small kernels are better than a single big high-performance kernel because of higher throughput and higher kernel frequency.

关键词： Accelerator FPGA OpenMP task-based programming

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PaRSEC: Scalability, flexibility, and hybrid architecture support for task-based applications in ECP

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2025年第1期39卷 147-166页

作者： Bouteiller, Aurelien Herault, Thomas Cao, Qinglei Schuchart, Joseph Bosilca, George Univ Tennessee Dept Elect Engn & Comp Sci 1122 Volunteer BlvdSuite 203 Knoxville TN 37996 USA St Louis Univ Dept Comp Sci St Louis MO USA Nvidia Corp Santa Clara CA USA

This paper highlights the most significant enhancements made to PaRSEC, a scalable task-based runtime system designed for hybrid machines, during the Exascale Computing Project (ECP). The enhancements focus on expanding the capabilities of PaRSEC to address the evolving landscape of parallel computing. Notable achievements include the integration of support for three major types of accelerators (NVIDIA, AMD, and Intel GPUs), the refinement and increased flexibility of the communication subsystem, and the introduction of new programming interfaces tailored for irregular applications. Additionally, the project resulted in the development of powerful debugging and performance analysis tools aimed at assisting users in understanding and optimizing their applications. We present a comprehensive demonstration of these advancements through a series of benchmarks and applications within ECP and beyond, thereby showcasing the enhanced capabilities of PaRSEC across the diverse architectures within the ECP, providing valuable insights into the runtime system's adaptability and performance across varied computing environments.

关键词： Exascale computing project task-based programming dataflow micro-tasks runtime

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Pushing the Boundaries of Small tasks: Scalable Low-Overhead Data-Flow programming in TTG

Pushing the Boundaries of Small Tasks: Scalable Low-Overhead...

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IEEE International Conference on Cluster Computing (CLUSTER)

作者： Schuchart, Joseph Nookala, Poornima Herault, Thomas Valeev, Edward F. Bosilca, George Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA SUNY Stony Brook Inst Adv Computat Sci Stony Brook NY 11794 USA Virginia Polytech Inst & State Univ Dept Chem Blacksburg VA 24061 USA

ISBN: (数字)9781665498562

ISBN: (纸本)9781665498562

Shared memory parallel programming models strive to provide low-overhead execution environments. task-based programming models, in particular, are well-suited to cope with the ubiquitous multi- and many-core systems since they allow applications to express all available concurrency to a scheduler, which is tasked with exploiting the available hardware resources. It is general consensus that atomic operations should be preferred over locks and mutexes to avoid inter-thread serialization and the resulting loss in efficiency. However, even atomic operations may serialize threads if not used judiciously. In this work, we will discuss several optimizations applied to TTG and the underlying PaRSEC runtime system aiming at removing contentious atomic operations to reduce the overhead of task management to a few hundred clock cycles. The result is an optimized data-flow programming system that seamlessly scales from a single node to distributed execution and which is able to compete with OpenMP in shared memory.

关键词： Dataflow graph Template task Graph PaRSEC TTG task-based programming

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Enabling FPGA and AI Engine tasks in the HPX programming Framework for Heterogeneous High-Performance Computing 20th

Enabling FPGA and AI Engine Tasks in the HPX Programming Fra...

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20th International Symposium on Applied Reconfigurable Computing (ARC)

作者： Kalkhof, Torben Heinz, Carsten Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9783031556722;9783031556739

The increasing complexity of modern exascale computers, with a growing number of cores per node, poses a challenge to traditional programming models. To address this challenge, Asynchronous Many-task (AMT) runtimes such as the C++-based HPX, divide computational problems into smaller tasks that are executed asynchronously by the runtime. By unifying the syntax and semantics of local and remote task execution, the scalability for distributed execution is enhanced. The asynchronous execution model conceals communication latency in distributed systems and eliminates global synchronization barriers, which improves the overall utilization of computation resources. While HPX and other AMT runtimes often support GPUs, there is still a lack of support for other accelerators, such as FPGAs, or more coarse-grained AI processing elements such as AMD's AI Engines (AIE). In this work, we extend the TaPaSCo framework so that TaPaSCo FPGA and AIE tasks can be transparently integrated into HPX applications. We show results for both microbenchmarks as well as the complete LULESH proxy HPC application to demonstrate this concept and evaluate the overheads. Both applications show that the combination of TaPaSCo and HPX can be efficiently used for cooperative computing between CPU software and FPGA/AIE hardware. Compared to CPU-only execution, we achieve a speedup of up to 2.4x in our stencil microbenchmark and a wall-clock speedup of 1.37x for the entire LULESH application, with 2.12x in the accelerated kernels itself. Our TaPaSCo/HPX integration is released as open-source.

关键词： FPGA task-based programming HPC AI engines

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PLASMA: Parallel Linear Algebra Software for Multicore Using OpenMP

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ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE 2019年第2期45卷 1–35页

作者： Dongarra, Jack Gates, Mark Haidar, Azzam Kurzak, Jakub Luszczek, Piotr Wu, Panruo Yamazaki, Ichitaro Yarkhan, Asim Abalenkovs, Maksims Bagherpour, Negin Hammarling, Sven Sistek, Jakub Stevens, David Zounon, Mawussi Relton, Samuel D. Univ Tennessee Dept Elect Engn & Comp Sci 1122 Volunteer BlvdSuite 203 Knoxville TN 37996 USA Univ Houston Dept Comp Sci 3551 Cullen Blvd Houston TX 77204 USA Univ Manchester Sch Math Manchester M13 9PL Lancs England Czech Acad Sci Inst Math Zitna 25 Prague 11567 Czech Republic Numer Algorithms Grp Manchester One53 Portland St Manchester M1 3LD Lancs England Univ Leeds Inst Hlth Sci Leeds LS2 9LJ W Yorkshire England

The recent version of the Parallel Linear Algebra Software for Multicore Architectures (PLASMA) library is based on tasks with dependencies from the OpenMP standard. The main functionality of the library is presented. Extensive benchmarks are targeted on three recent multicore and manycore architectures, namely, an Intel Xeon, Intel Xeon Phi, and IBM POWER 8 processors.

关键词： Numerical linear algebra libraries tile algorithms task-based programming multicore processors OpenMP PLASMA

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An asynchronous and task-based implementation of peridynamics utilizing HPX-the C++ standard library for parallelism and concurrency

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SN APPLIED SCIENCES 2020年第12期2卷 1-21页

作者： Diehl, Patrick Jha, Prashant K. Kaiser, Hartmut Lipton, Robert Levesque, Martin Louisiana State Univ Ctr Computat & Technol Baton Rouge LA 70803 USA Univ Texas Austin Oden Inst Computat Engn & Sci Austin TX 78712 USA Louisiana State Univ Dept Math Baton Rouge LA 70803 USA Polytech Montreal Dept Multi Scale Mech Montreal PQ Canada

On modern supercomputers, asynchronous many task systems are emerging to address the new architecture of computational nodes. Through this shift of increasing cores per node, a new programming model with focus on handling of the fine-grain parallelism with increasing amount of cores per computational node is needed. Asynchronous Many task (AMT) run time systems represent a paradigm for addressing the fine-grain parallelism. They handle the increasing amount of threads per node and concurrency. HPX, a open source C++ standard library for parallelism and concurrency, is one AMT which is conforming to the C++ standard. Motivated by the impressive performance of asynchronous task-based parallelism through HPX to N-body problem and astrophysics simulation, in this work, we consider its application to the Peridynamics theory. Peridynamics is a non-local generalization of continuum mechanics tailored to address discontinuous displacement fields arising in fracture mechanics. Peridynamics requires considerable computing resources, owing to its non-local nature of formulation, offering a scope for improved computing performance via asynchronous task-based parallelism. Our results show that HPX-based peridynamic computation is scalable, and the scalability is in agreement with the theory. In addition to the scalability, we also show the validation results and the mesh convergence results. For the validation, we consider implicit time integration and compare the result with the classical continuum mechanics (CCM) (peridynamics under small deformation should give similar results as CCM). For the mesh convergence, we consider explicit time integration and show that the results are in agreement with theoretical claims in previous works.

关键词： Peridynamics finite difference approximation concurrency parallelization HPX task-based programming asynchronous many task systems

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An execution environment for flexible task-oriented software on multicore systems

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CONCURRENT ENGINEERING-RESEARCH AND APPLICATIONS 2012年第2期20卷 161-173页

作者： Rauber, Thomas Ruenger, Gudula Univ Bayreuth Dept Comp Sci Bayreuth Germany Tech Univ Chemnitz Dept Comp Sci Chemnitz Germany

The article addresses the challenges of software development for current and future parallel computers, which are expected to be dominated by multicore and many-core architectures. Using these multicore processors for cluster systems will create systems with thousands of cores and deep memory hierarchies. To efficiently exploit the tremendous parallelism of these hardware platforms, a new generation of programming methodologies is needed. This article proposes a parallel programming methodology exploiting a task-based representation of application software. For the specification of task-based programs, a coordination language is presented, which uses external variables to express the cooperation between tasks. For the actual execution of a task-based program on a specific parallel architecture, different dynamic scheduling algorithms embedded into an execution environment are introduced. Runtime experiments for complex methods from a numerical analysis are performed on different parallel execution platforms.

关键词： task-based programming coordination language scheduling parallel execution mapping

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Dynamic task Fusion for a Block-Structured Finite Volume Solver over a Dynamically Adaptive Mesh with Local Time Stepping 37th

Dynamic Task Fusion for a Block-Structured Finite Volume Sol...

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37th International Supercomputing Conference on High Performance Computing (ISC High Performance Computing)

作者： Li, Baojiu Schulz, Holger Weinzierl, Tobias Zhang, Han Univ Durham Inst Computat Cosmol Durham DH1 3FE England Univ Durham Dept Comp Sci Durham DH1 3FE England Univ Durham Large Scale Comp Inst Data Sci Durham DH1 3FE England

ISBN: (纸本)9783031073120;9783031073113

Load balancing of generic wave equation solvers over dynamically adaptive meshes with local time stepping is difficult, as the load changes with every time step. task-based programming promises to mitigate the load balancing problem. We study a Finite Volume code over dynamically adaptive block-structured meshes for two astrophysics simulations, where the patches (blocks) define tasks. They are classified into urgent and low priority tasks. Urgent tasks are algorithmically latency-sensitive. They are processed directly as part of our bulk-synchronous mesh traversals. Non-urgent tasks are held back in an additional task queue on top of the task runtime system. If they lack global side-effects, i.e. do not alter the global solver state, we can generate optimised compute kernels for these tasks. Furthermore, we propose to use the additional queue to merge tasks without side-effects into task assemblies, and to balance out imbalanced bulk synchronous processing phases.

关键词： task-based programming Block-structured dynamic adaptive mesh refinement Local time stepping Wave equation solvers

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task-based Cholesky Decomposition on Knights Corner Using OpenMP

Task-Based Cholesky Decomposition on Knights Corner Using Op...

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International Supercomputing Conference (ISC High Performance)

作者： Dorris, Joseph Kurzak, Jakub Luszczek, Piotr YarKhan, Asim Dongarra, Jack Innovat Comp Lab Knoxville TN 37996 USA

ISBN: (纸本)9783319460796;9783319460789

The growing popularity of the Intel Xeon Phi coprocessors and the continued development of this new many-core architecture have created the need for an open-source, scalable, and cross-platform taskbased dense linear algebra package that can efficiently use this type of hardware. In this paper, we examined the design modifications necessary when porting PLASMA, a task-based dense linear algebra library, to run effectively on Intel's Knights Corner Xeon Phi coprocessor. First, we modified PLASMA's tiled Cholesky decomposition to use OpenMP for its scheduling mechanism to enable Xeon Phi compatibility. We then compared the performance of our modified code to that of the original dynamic scheduler running on an Intel Xeon Sandy Bridge CPU. Finally, we looked at the performance of the new OpenMP tiled Cholesky decomposition on a Knights Corner coprocessor. We found that desirable performance for this architecture was attainable with the right code optimizations;these changes were necessary to account for differences in the runtimes and in the hardware itself.

关键词： Cholesky decomposition Linear algebra OpenMP PLASMA task-based programming Tile algorithms Xeon Phi

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