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作者： Bak, Seonmyeong Georgia Tech

学位级别：博士

On-node parallelism has increased significantly in high-performance computing systems. This huge amount of parallelism can be used to speed up regular paral- lel applications relatively easily because straightforward approaches usually suffice to map their computation patterns and data layouts on to available on-node parallelism. However, irregular parallel applications require considerable effort to run on the mod- ern processors with massive amounts of intra-node parallelism. Parallel programming models and runtime approaches have been proposed to help programmers to write those applications quickly, but it’s still not easy to write efficient irregular paral- lel applications. Two key challenges in mapping irregular applications onto on-node parallelism are load balance and computation-communication overlap. In this thesis proposal, we address these challenges through new runtime approaches and new APIs that enable users to provide minimal information for application-aware scheduling. First, we introduce new algorithms to improve the scheduling of irregular task graphs containing a mix of communication and computation tasks with data-parallelism and blocking operations. We combine gang-scheduling with work-stealing for data- parallel tasks with frequent inter/intra-node communication in the task graphs so as to reduce interference and expensive context switching operations. We also propose improved victim selection policies for work-stealing to improve the load balance and overlap of ready tasks that have child tasks. Next, we propose an efficient integrated runtime system to handle load balancing of irregular applications written in hybrid parallel programming models. We introduce a unified runtime system that integrates distributed and shared-memory programming, as exemplified by the combination of Charm++ and OpenMP. In this approach, all processing resources (cores) can be used flexibly across both the distributed and shared-memory levels, thereby enabling mor

关键词： High Performance Computing Runtime Systems Load Balancing task-based programming models

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A Linux Kernel Scheduler Extension for Multi-Core Systems 26

A Linux Kernel Scheduler Extension for Multi-Core Systems

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26th International Conference on High Performance Computing, Data and Analytics (HiPCW)

作者： Roca, Aleix Rodriguez, Samuel Segura, Albert Marquet, Kevin Beltran, Vicenc Barcelona Supercomp Ctr Jordi Girona 29-31 Barcelona 08034 Spain Univ Lyon INSA Lyon INRIA CITI 6 Ave Arts F-69621 Villeurbanne France

ISBN: (纸本)9781728145358

The Linux kernel is mostly designed for multi-programed environments, but high-performance applications have other requirements. Such applications are run standalone, and usually rely on runtime systems to distribute the application's workload on worker threads, one per core. However, due to current OSes limitations, it is not feasible to track whether workers are actually running or blocked due to, for instance, a requested resource. For I/O intensive applications, this leads to a significant performance degradation given that the core of a blocked thread becomes idle until it is able to run again. In this paper, we present the proof-of-concept of a Linux kernel extension denoted User-Monitored Threads (UMT) which tackles this problem. Our extension allows a user-space process to be notified of when the selected threads become blocked or unblocked, making it possible for a runtime to schedule additional work on the idle core. We implemented the extension on the Linux Kernel 5.1 and adapted the Nanos6 runtime of the OmpSs-2 programming model to take advantage of it. The whole prototype was tested on two applications which, on the tested hardware and the appropriate conditions, reported speedups of almost 2x.

关键词： Linux Kernel Scheduler task-based programming models I/O HPC

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Introducing the task-Aware Storage I/O (TASIO) Library 15th

Introducing the Task-Aware Storage I/O (TASIO) Library

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15th International Workshop on OpenMP (IWOMP)

作者： Roca Nonell, Aleix Beltran Querol, Vicenc Mateo Bellido, Sergi Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9783030285968;9783030285951

task-based programming models are excellent tools to parallelize and seamlessly load balance an application workload. However, the integration of I/O intensive applications and task-based programming models is lacking. Typically, I/O operations stall the requesting thread until the data is serviced by the backing device. Because the core where the thread was running becomes idle, it should be possible to overlap the data query operation with either computation workloads or even more I/O operations. Nonetheless, overlapping I/O tasks with other tasks entails an extra degree of complexity currently not managed by programming models' runtimes. In this work, we focus on integrating storage I/O into the tasking model by introducing the task-Aware Storage I/O (TASIO) library. We test TASIO extensively with a custom benchmark for a number of configurations and conclude that it is able to achieve speedups up to 2x depending on the workload, although it might lead to slowdowns if not used with the right settings.

关键词： task-based programming models I/O OmpSs-2 OpenMP HPC

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Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2018年第5期29卷 1174-1187页

作者： Caheny, Paul Alvarez, Lluc Derradji, Said Valero, Mateo Moreto, Miquel Casas, Marc UPC BSC Barcelona 08034 Spain UPC Dept Arquitectura Comp Barcelona 08034 Spain Bull Atos Grp F-79450 Les Clayes Sous Bois France

Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on- and off-chip traffic in the system. This paper analyses how coherence traffic may be best constrained in a large, real ccNUMA platform comprising 288 cores through the use of a joint hardware/software approach. For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data allocation techniques to make most efficient use of the added hardware. The effectiveness of this joint approach is demonstrated by speedups of 3.14x to 9.97x and coherence traffic reductions of up to 99 percent in comparison to NUMA-oblivious scheduling and data allocation.

关键词： Cache coherence NUMA task-based programming models

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Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling 16

Reducing Cache Coherence Traffic with Hierarchical Directory...

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International Conference on Parallel Architectures and Compilation (PACT)

作者： Caheny, Paul Casas, Marc Moreto, Miguel Gloaguen, Herve Saintes, Maxime Ayguade, Eduard Labarta, Jesus Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Dept Arquitectura Comp Barcelona Spain Bull Atos Technol Les Clayes Sous Bois France

ISBN: (纸本)9781450341219

Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on-and off-chip traffic in the system. This paper analyses how coherence traffic may be best constrained in a large, real ccNUMA platform through the use of a joint hardware/software approach. For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data allocation techniques to make most efficient use of the added hardware. The effectiveness of this joint approach is demonstrated by speedups of 1.23x to 2.54x and coherence traffic reductions between 44% and 77% in comparison to NUMA-oblivious scheduling and data allocation. Furthermore, we show that the NUMA-aware techniques we employ at the runtime level are crucial to ensure the added hierarchical layer in the directory coherence protocol does not introduce significant coherence traffic to the system.

关键词： Cache Coherence NUMA task-based programming models

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PARSECSs: Evaluating the Impact of task Parallelism in the PARSEC Benchmark Suite

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2016年第4期12卷 41-41页

作者： Chasapis, Dimitrios Casas, Marc Moreto, Miquel Vidal, Raul Ayguade, Eduard Labarta, Jesus Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna BarcelonaTech Barcelona Spain

In this work, we show how parallel applications can be implemented efficiently using task parallelism. We also evaluate the benefits of such parallel paradigm with respect to other approaches. We use the PARSEC benchmark suite as our test bed, which includes applications representative of a wide range of domains from HPC to desktop and server applications. We adopt different parallelization techniques, tailored to the needs of each application, to fully exploit the task-based model. Our evaluation shows that task parallelism achieves better performance than thread-based parallelization models, such as Pthreads. Our experimental results show that we can obtain scalability improvements up to 42% on a 16-core system and code size reductions up to 81%. Such reductions are achieved by removing from the source code application specific schedulers or thread pooling systems and transferring these responsibilities to the runtime system software.

关键词： Performance Measurement Experimentation Parallel Applications scalable applications parallel benchmarks parallel architectures parallel runtime systems task-based programming models concurrency synchronization

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Runtime-Guided Management of Scratchpad Memories in Multicore Architectures 24

Runtime-Guided Management of Scratchpad Memories in Multicor...

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24th International Conference on Parallel Architecture and Compilation (PACT)

作者： Alvarez, Lluc Moreto, Miquel Casas, Marc Castillo, Emilio Martorell, Xavier Labarta, Jesus Ayguade, Eduard Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Dept Arquitectura Computadors Barcelona Spain

ISBN: (纸本)9781467395243

The increasing number of cores and the anticipated level of heterogeneity in upcoming multicore architectures cause important problems in traditional cache hierarchies. A good way to alleviate these problems is to add scratchpad memories alongside the cache hierarchy, forming a hybrid memory hierarchy. This memory organization has the potential to improve performance and to reduce the power consumption and the on-chip network traffic, but exposing such a complex memory model to the programmer has a very negative impact on the programmability of the architecture. Emerging task-based programming models are a promising alternative to program heterogeneous multicore architectures. In these models the runtime system manages the execution of the tasks on the architecture, allowing them to apply many optimizations in a generic way at the runtime system level. This paper proposes giving the runtime system the responsibility to manage the scratchpad memories of a hybrid memory hierarchy in multicore processors, transparently to the programmer. In the envisioned system, the runtime system takes advantage of the information found in the task dependences to map the inputs and outputs of a task to the scratchpad memory of the core that is going to execute it. In addition, the paper exploits two mechanisms to overlap the data transfers with computation and a locality-aware scheduler to reduce the data motion. In a 32-core multicore architecture, the hybrid memory hierarchy outperforms cache-only hierarchies by up to 16%, reduces on-chip network traffic by up to 31% and saves up to 22% of the consumed power.

关键词： Scratchpad memories task-based programming models

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On the application task granularity and the interplay with the scheduling overhead in many-core shared memory systems

On the application task granularity and the interplay with t...

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IEEE International Conference on Cluster Computing (CLUSTER)

作者： Akhmetova, Dana Kestor, Gokcen Gioiosa, Roberto Markidis, Stefano Laure, Erwin Pacific NW Natl Lab High Performance Comp Richland WA 99352 USA KTH Royal Inst Technol High Performance Comp & Visualizat Dept Stockholm Sweden

ISBN: (纸本)9781467365987

task-based programming models are considered one of the most promising programming model approaches for exascale supercomputers because of their ability to dynamically react to changing conditions and reassign work to processing elements. One question, however, remains unsolved: what should the task granularity of task-based applications be? Finegrained tasks offer more opportunities to balance the system and generally result in higher system utilization. However, they also induce in large scheduling overhead. The impact of scheduling overhead on coarse-grained tasks is lower, but large systems may result imbalanced and underutilized. In this work we propose a methodology to analyze the interplay between application task granularity and scheduling overhead. Our methodology is based on three main points: 1) a novel task algorithm that analyzes an application directed acyclic graph (DAG) and aggregates tasks;2) a fast and precise emulator to analyze the application behavior on systems with up to 1,024 cores;3) a comprehensive sensitivity analysis of application performance and scheduling overhead breakdown. Our results show that there is an optimal task granularity between 1.2x10(4) and 10x10(4) cycles for the representative schedulers. Moreover, our analysis indicates that a suitable scheduler for exascale task-based applications should employ a best-effort local scheduler and a sophisticated remote scheduler to move tasks across worker threads.

关键词： directed graphs multi-threading processor scheduling shared memory systems DAG aggregates tasks application behavior application task granularity coarse-grained tasks directed acyclic graph exascale supercomputers exascale task-based applications fine-grained tasks local scheduler many-core shared memory systems processing elements programming model approaches remote scheduler scheduling overhead breakdown sensitivity analysis system utilization task algorithm task-based programming models worker threads Aggregates Processor scheduling programming Runtime Scalability Scheduling Synchronization scheduling overhead task granularity task-based schedulers scheduling of multiprocessor Program Behavior shared memory systems Directed Acyclic Graph Multithreading directed graphs Runtime programming application task Scalability Sensitivity analysis

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Criticality-Aware Dynamic task Scheduling for Heterogeneous Architectures 15

Criticality-Aware Dynamic Task Scheduling for Heterogeneous ...

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29th ACM International Conference on Supercomputing (ICS)

作者： Chronaki, Kallia Rico, Alejandro Badia, Rosa M. Ayguade, Eduard Labarta, Jesus Valero, Mateo Barcelona Supercomp Ctr Barcelona Spain CSIC Artificial Intelligence Res Inst IIIA Barcelona Spain Univ Politecn Cataluna BarcelonaTech Barcelona Spain

ISBN: (纸本)9781450335591

Current and future parallel programming models need to be portable and efficient when moving to heterogeneous multi-core systems. OmpSs is a task-based programming model with dependency tracking and dynamic scheduling. This paper describes the OmpSs approach on scheduling dependent tasks onto the asymmetric cores of a heterogeneous system. The proposed scheduling policy improves performance by prioritizing the newly-created tasks at runtime, detecting the longest path of the dynamic task dependency graph, and assigning critical tasks to fast cores. While previous works use profiling information and are static, this dynamic scheduling approach uses information that is discoverable at runtime which makes it implementable and functional without the need of an oracle or profiling. The evaluation results show that our proposal outperforms a dynamic implementation of Heterogeneous Earliest Finish Time by up to 1.15x, and the default breadth-first OmpSs scheduler by up to 1.3x in an 8-core heterogeneous platform and up to 2.7x in a simulated 128-core chip.

关键词： High performance computing Scheduling Heterogeneous systems task-based programming models

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Evaluating Execution Time Predictability of task-based Programs on Multi-Core Processors

Evaluating Execution Time Predictability of Task-Based Progr...

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20th Euro-Par International Workshops

作者： Grass, Thomas Rico, Alejandro Casas, Marc Moreto, Miquel Ramirez, Alex Univ Politecn Cataluna ES-08034 Barcelona Spain Barcelona Supercomp Ctr Barcelona 08034 Spain

ISBN: (纸本)9783319143132;9783319143125

task-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the same code, which leads us to the hypothesis that their performance should be regular and thus their execution time should be predictable. We evaluate this hypothesis for a set of 12 task-based programs on 4 different machines: a high-end Intel Sandy-Bridge, an IBM POWER7, an ARM Cortex-A9 and an ARM Cortex-A15. We show, that predicting execution time assuming performance regularity can lead to errors of up to 92%. We identify and analyze three sources of execution time impredictability: input dependence, multiple behaviors per task type and resource sharing. We present two models based on linear interpolation and clustering, reducing the prediction error to less than 12% for input dependent task types and to less than 2% for task types with multiple classes of behavior. All in all, this work invalidates the assumption that performance is always regular across instances of the same task type and quantifies its variability on a wide range of benchmarks and multi-core systems.

关键词： Execution Time Predictability task-based programming models Multi-Core

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