检索结果-内蒙古大学图书馆

IEEE International Conference on Cluster Computing (CLUSTER)

作者： Choudhury, Olivia Rajan, Dinesh Hazekamp, Nicholas Gesing, Sandra Thain, Douglas Emrich, Scott Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

ISBN: (纸本)9781467365987

The runtime configuration of parallel and distributed applications remains a mysterious art. To tune an application on a particular system, the end-user must choose the number of machines, the number of cores per task, the data partitioning strategy, and so on, all of which result in a combinatorial explosion of choices. While one might try to exhaustively evaluate all choices in search of the optimal, the end user's goal is simply to run the application once with reasonable performance by avoiding terrible configurations. To address this problem, we present a hybrid technique based on regression models for tuning data intensive bioinformatics applications: the sequential computational kernel is characterized empirically and then incorporated into an ab initio model of the distributed system. We demonstrate this technique on the commonly-used applications BWA, Bowtie2, and BLASR and validate the accuracy of our proposed models on clouds and clusters.

关键词： bioinformatics cloud computing multi-threading parallel processing regression analysis bioinformatics application cluster computing data-intensive workload distributed application hybrid technique parallel application regression model task-level parallelism thread-level parallelism Bioinformatics Computational modeling Data models Genomics Instruction sets Parallel processing Predictive models cluster and cloud computing distributed and parallel computing genome alignment predictive modeling PARALLEL PROCESSING (COMPUTERS) Bioinformatics Cloud Computing simple regression (model) Prediction models instruction sets Multithreading data models cluster computing Computational modeling Clouds Genomics regression analysis

来源：评论

学校读者我要写书评

暂无评论

Multi-Objective Aware Extraction of task-level parallelism Using Genetic Algorithms

Multi-Objective Aware Extraction of Task-Level Parallelism U...

引用

Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Cordes, Daniel Marwedel, Peter TU Dortmund Univ Dortmund Germany

ISBN: (纸本)9783981080186

A large amount of research work has been done in the area of automatic parallelization for decades, resulting in a huge amount of tools, which should relieve the designer from the burden of manually parallelizing an application. Unfortunately, most of these tools are only optimizing the execution time by splitting up applications into concurrently executed tasks. In the domain of embedded devices, however, it is not sufficient to look only at this criterion. Since most of these devices are constraint-driven regarding execution time, energy consumption, heat dissipation and other objectives, a good trade-off has to be found to efficiently map applications to multiprocessor system on chip (MPSoC) devices. Therefore, we developed a fully automated multi-objective aware parallelization framework, which optimizes different objectives at the same time. The tool returns a Pareto-optimal front of solutions of the parallelized application to the designer, so that the solution with the best trade-off can be chosen.

关键词： Automatic Parallelization Embedded Software Multi-Objective Genetic Algorithms task-level parallelism Energy awareness

来源：评论

学校读者我要写书评

暂无评论

COSPlay: Leveraging task-level parallelism for High-Throughput Synchronous Persistence 21

COSPlay: Leveraging Task-Level Parallelism for High-Throughp...

引用

54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Vemmou, Marina Daglis, Alexandros Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9781450385572

A key challenge in programming crash-consistent applications for Persistent Memory (PM) is achieving high performance while controlling the order of PM updates. Managing persist ordering from the CPU typically requires frequent synchronization points, which expose the PM's high persist latency on the execution's critical path. To mitigate this overhead, prior proposals relax the persistency model and decouple persistence from the program's volatile execution, delegating persistence ordering to specialized hardware mechanisms such that persistent state lags behind volatile state. In this work, we identify the opportunity to mitigate the effect of persist latency by leveraging the task-level parallelism available in many PM applications, while preserving the stricter semantics of synchronous persistence and the familiar x86 persistency model. We introduce COSPlay, a software-hardware co-design that employs coroutines and rapid userspace context switching to hide persist latency by overlapping persist operations across concurrent tasks. Modest CPU extensions enable the hardware to fully overlap persists of different contexts, while preserving intra-context ordering to meet crash consistency requirements. COSPlay boosts the throughput of crash-consistent applications by up to 1.7x on systems with basic PM support. For systems with higher persist latency due to added backend memory operations, such as encryption and deduplication, COSPlay's performance gains grow to 2.2 - 7.3x.

关键词： persistent memory persist ordering crash consistency task-level parallelism coroutines

来源：评论

学校读者我要写书评

暂无评论

Energy-efficient multiprocessor systems-on-chip for embedded computing: Exploring programming models and their architectural support

引用

IEEE TRANSACTIONS ON COMPUTERS 2007年第5期56卷 606-621页

作者： Poletti, Francesco Poggiali, Antonio Bertozzi, Davide Benini, Luca Marchal, Pol Loghi, Mirko Poncino, Massimo Univ Bologna DEIS I-40100 Bologna Italy STMicroelectronics Ctr Direz Colleoni I-20041 Agrate Brianza MI Italy Univ Ferrara Dept Engn I-44100 Ferrara Italy ESAT KULeuven IMEC vzw B-3001 Heverlee Belgium Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

In today's multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities and to achieve the 100 Gops/W energy efficiency target required for Ambient Intelligence Applications. However, mapping abstract programming models onto tightly power-constrained hardware architectures imposes overheads which might seriously compromise performance and energy efficiency. The objective of this work is to perform a comparative analysis of message passing versus shared memory as programming models for single-chip multiprocessor platforms. Our analysis is carried out from a hardware-software viewpoint: We carefully tune hardware architectures and software libraries for each programming model. We analyze representative application kernels from the multimedia domain, and identify application-level parameters that heavily influence performance and energy efficiency. Then, we formulate guidelines for the selection of the most appropriate programming model and its architectural support.

关键词： MPSoCs embedded multimedia programming models task-level parallelism energy efficiency low power

来源：评论

学校读者我要写书评

暂无评论

Exploiting thread-level parallelism in the iterative solution of sparse linear systems

引用

PARALLEL COMPUTING 2011年第3期37卷 183-202页

作者： Aliaga, Jose I. Bollhoefer, Matthias Martin, Alberto F. Quintana-Orti, Enrique S. Univ Jaime I Dpto Ingn & Ciencia Comp Castellon de La Plana 12071 Spain Tech Univ Carolo Wilhelmina Braunschweig Inst Computat Math D-38106 Braunschweig Germany

We investigate the efficient iterative solution of large-scale sparse linear systems on shared-memory multiprocessors. Our parallel approach is based on a multilevel ILU preconditioner which preserves the mathematical semantics of the sequential method in ILU-PACK. We exploit the parallelism exposed by the task tree corresponding to the nested dissection hierarchy (task parallelism), employ dynamic scheduling of tasks to processors to improve load balance, and formulate all stages of the parallel PCG method conformal with the computation of the preconditioner to increase data reuse. Results on a CC-NUMA platform with 16 processors reveal the parallel efficiency of this solution. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Large sparse linear systems Factorization-based preconditioning Preconditioned conjugate gradients task-level parallelism Shared-memory multiprocessors

来源：评论

学校读者我要写书评

暂无评论

Towards enhanced MRI by using a multiple back end programming framework

引用

FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2020年 112卷 467-477页

作者： Garcia-Blas, Javier Astorga, David del Rio Carretero, Jesus Garcia, J. Daniel Univ Carlos III Madrid Madrid Spain

In recent years, on-line processing of data streams (DaSP) has been established as a major computing paradigm. This is due mainly to two reasons: first, more and more data that are generated in near real-time need to be processed;the second reason is given by the need of efficient parallel applications. However, the above-mentioned areas expose a tough challenge over traditional data-analysis techniques, which have been forced to evolve to a stream perspective. In this work, we apply a novel multiple back end programming framework for stream data and task based parallelism to a multi-staged diffusion magnetic resonance imaging (MRI) toolkit, named pHARDI. The results demonstrate the benefits of using our framework in terms of performance and memory usage. The evaluation carried out also depicts that the speed-up of our parallel framework increases with the problem size. (c) 2020 Elsevier B.V. All rights reserved.

关键词： Data stream processing GRPPI task-level parallelism Data-level parallelism MRI reconstruction

来源：评论

学校读者我要写书评

暂无评论

Run-time support for the automatic parallelization of Java programs

引用

JOURNAL OF SUPERCOMPUTING 2004年第1期28卷 91-117页

作者： Chan, B Abdelrahman, TS Univ Toronto Dept Elect & Comp Engn Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

We describe and evaluate a novel approach for the automatic parallelization of programs that use pointer-based dynamic data structures, written in Java. The approach exploits parallelism among methods by creating an asynchronous thread of execution for each method invocation in a program. At compile time, methods are analyzed to determine the data they access, parameterized by their context. A description of these data accesses is transmitted to a run-time system during program execution. The run-time system utilizes this description to determine when a thread may execute, and to enforce dependences among threads. This run-time system is the main focus of this paper. More specifically, the paper details the representation of data accesses in a method and the framework used by the run-time system to detect and enforce dependences among threads. Experimental evaluation of an implementation of the run-time system on a four-processor Sun multiprocessor indicates that close to ideal speedup can be obtained for a number of benchmarks. This validates our approach.

关键词： automatic parallelization parallelizing compilers Java optimizations run-time parallelization task-level parallelism

来源：评论

学校读者我要写书评

暂无评论

Exploiting task parallelism with OpenCL: A Case Study

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2019年第1期91卷 33-46页

作者： Jaaskelainen, Pekka Korhonen, Ville Koskela, Matias Takala, Jarmo Egiazarian, Karen Danielyan, Aram Cruz, Cristovao Price, James McIntosh-Smith, Simon Tampere Univ Technol Tampere Finland Tampere Univ Technol Customized Parallel Comp CPC Grp Tampere Finland Noiseless Imaging Ltd Tampere Finland Univ Bristol High Performance Comp Bristol Avon England

While data parallelism aspects of OpenCL have been of primary interest due to the massively data parallel GPUs being on focus, OpenCL also provides powerful capabilities to describe task parallelism. In this article we study the task parallel concepts available in OpenCL and find out how well the different vendor-specific implementations can exploit task parallelism when the parallelism is described in various ways utilizing the command queues. We show that the vendor implementations are not yet capable of extracting kernel-level task parallelism from in-order queues automatically. To assess the potential performance benefits of in-order queue parallelization, we implemented such capabilities to an open source implementation of OpenCL. The evaluation was conducted by means of a case study of an advanced noise reduction algorithm described as a multi-kernel OpenCL application.

关键词： OpenCL task-level parallelism

来源：评论

学校读者我要写书评

暂无评论

Performance and energy effects on task-based parallelized applications

引用

JOURNAL OF SUPERCOMPUTING 2018年第6期74卷 2627-2637页

作者： Caminal, Helena Caballero, Diego Cebrian, Juan M. Ferrer, Roger Casas, Marc Moreto, Miquel Martorell, Xavier Valero, Mateo Cornell Univ Comp Syst Lab Ithaca NY 14853 USA BSC Barcelona Spain UPC Barcelona Spain

Heterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a huge challenge due to the ever-increasing architecture complexity. task-based environments hide most of this complexity, improving scalability and usage of the available resources. In these environments, while there has been a lot of effort to ease parallelization and improve the usage of heterogeneous resources, vectorization has been considered a secondary objective. Furthermore, there has been a swift and unstoppable burst of vector architectures at all market segments, from embedded to HPC. Vectorization can no longer be ignored, but manual vectorization is tedious, error-prone and not practical for the average programmer. This work evaluates the feasibility of user-directed vectorization in task-based applications. Our evaluation is based on the OmpSs programming model, extended to support user-directed vectorization for different SIMD architectures (i.e., SSE, AVX2, AVX512). Results show that user-directed codes achieve manually optimized code performance and energy efficiency with minimal code modifications, favoring portability across different SIMD architectures.

关键词： Data-level parallelism task-level parallelism Vectorization Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Optimizing image processing on multi-core CPUs with Intel parallel programming technologies

引用

MULTIMEDIA TOOLS AND APPLICATIONS 2014年第2期68卷 237-251页

作者： Kim, Cheong Ghil Kim, Jeom Goo Lee, Do Hyeon Namseoul Univ Dept Comp Sci Cheonan 331707 Choongnam South Korea Namseoul Univ IT Convergence Technol Res & Educ Ctr Cheonan 331707 Choongnam South Korea

The rapid advance of computer hardware and popularity of multimedia applications enable multi-core processors with sub-word parallelism instructions to become a dominant market trend in desk-top PCs as well as high end mobile devices. This paper presents an efficient parallel implementation of 2D convolution algorithm demanding high performance computing power in multi-core desktop PCs. It is a representative computation intensive algorithm, in image and signal processing applications, accompanied by heavy memory access;on the other hand, their computational complexities are relatively low. The purpose of this study is to explore the effectiveness of exploiting the streaming SIMD (Single Instruction Multiple Data) extension (SSE) technology and TBB (Threading Building Block) run-time library in Intel multi-core processors. By doing so, we can take advantage of all the hardware features of multi-core processor concurrently for data-and task-level parallelism. For the performance evaluation, we implemented a 3x3 kernel based convolution algorithm using SSE2 and TBB with different combinations and compared their processing speeds. The experimental results show that both technologies have a significant effect on the performance and the processing speed can be greatly improved when using two technologies at the same time;for example, 6.2, 6.1, and 1.4 times speedup compared with the implementation of either of them are suggested for 256x256, 512x512, and 1024x1024 data sets, respectively.

关键词： Multi-core Streaming SIMD extension Threading building block Sobel operator Sub-word parallelism task-level parallelism Multimedia

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：