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Compressed test pattern generation for Deep Neural Networks

IEEE TRANSACTIONS ON COMPUTERS 2025年第1期74卷 307-315页

作者： Moussa, Dina A. Hefenbrock, Michael Tahoori, Mehdi Karlsruhe Inst Technol KIT D-76131 Karlsruhe Germany Arab Acad Sci Technol & Maritime Transport Cairo 2033 Egypt RevoAI GmbH D-76131 Karlsruhe Germany

Deep neural networks (DNNs) have emerged as an effective approach in many artificial intelligence tasks. Several specialized accelerators are often used to enhance DNN's performance and lower their energy costs. However, the presence of faults can drastically impair the performance and accuracy of these accelerators. Usually, many test patterns are required for certain types of faults to reach a target fault coverage, which in turn hence increases the testing overhead and storage cost, particularly for in-field testing. For this reason, compression is typically done after test generation step to reduce the storage cost for the generated test patterns. However, compression is more efficient when considered in an earlier stage. This paper generates the test pattern in a compressed form to require less storage. This is done by generating all test patterns as a linear combination of a set of jointly used test patterns (basis), for which only the coefficients need to be stored. The fault coverage achieved by the generated test patterns is compared to that of the adversarial and randomly generated test images. The experimental results showed that our proposed test pattern outperformed and achieved high fault coverage (up to 99.99%) and a high compression ratio (up to 307.2x).

关键词： Artificial neural networks Neurons Circuit faults Vectors testing test pattern generators Costs Deep neural networks functional faults test pattern generation test compression

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test pattern generation and signature analysis for burst errors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1998年第3期45卷 410-414页

作者： Katti, RS N Dakota State Univ Dept Elect Engn Fargo ND 58105 USA

In testing certain systems, checking for burst errors is important, This is due to the fact that errors are confined to a certain number of bits. If signature analysis is used to test a circuit then the testing capabilities depend on the polynomial that defines the linear feedback shift register (LFSR) used in the test. In this paper we show that the LFSR that is suitable for checking for burst errors is not suitable for test pattern generation, We propose a method to modify the LFSR that performs signature analysis efficiently into a nonlinear feedback shift register (NLFSR) that is suitable for test pattern generation.

关键词： burst errors error detection shift registers signature analysis test pattern generation

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test pattern generation and Critical Path Selection in the Presence of Statistical Delays

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第1期28卷 163-173页

作者： Javvaji, Pavan Kumar Tragoudas, Spyros Southern Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths.

关键词： Delays Logic gates Probability Integrated circuit modeling Automatic test pattern generation Correlation Very large scale integration Critical path selection delay modeling path delay faults path sensitization test pattern generation

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test pattern generation for Static Burn-in Based on Equivalent Fault Model

Test Pattern Generation for Static Burn-in Based on Equivale...

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IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

作者： Cui, Xiaole Qian, Zhengyu Shi, Xinming Lee, Chung-Len Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen Peoples R China

ISBN: (纸本)9781467325233

To speed up the deterioration of a circuit under test ( CUT), an input pattern is needed to maximize its leakage power in the static burn-in process. This paper presents an efficient pattern generation method with ATPG approach. To reduce the effort of precise power calculation, a metric that is linearly related to the leakage power of CUT is proposed. This generation method reuses the test set for stuck-at faults, and it can search for the quasi-optimal target pattern in the collapsed pattern space by the equivalent fault model.

关键词： static burn-in test pattern generation leakage power fault model

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test pattern generation to Detect Multiple Faults in ROBDD based Combinational Circuits 23

Test Pattern Generation to Detect Multiple Faults in ROBDD b...

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23rd IEEE International Symposium on On-Line testing and Robust System Design (IOLTS)

作者： Shah, Toral Matrosova, Anzhela Singh, Virendra Indian Inst Technol Dept Elect Engn CADSL Bombay Maharashtra India Tomsk State Univ Dept Appl Math & Cybernat Tomsk Russia

ISBN: (纸本)9781538603529

Reduced Ordered Binary Decision Diagram (ROBDD) based circuit syntheses is known to have complete testability under single stuck-at, multiple stuck-at and path delay fault models. In this paper we propose a test generation methodolgy for ROBDD based implementations. The test vectors required for all multiple stuck-at faults and delay faults are derived from the disjoint sum-of-products(DSOPs) representation thereby allowing test generation at design time with minimum effort.

关键词： ROBDD combinational logic test pattern generation

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test pattern generation for Multiple Victim Lines of Crosstalk Effect in Digital Circuits by Binary Decision Diagram 2nd

Test Pattern Generation for Multiple Victim Lines of Crossta...

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International Conference on Electrical and Information Technologies for Rail Transportation - Electrical Traction

作者： Pan, Zhongliang Chen, Ling S China Normal Univ Sch Phys & Telecommun Engn Guangzhou 510006 Guangdong Peoples R China

ISBN: (纸本)9783662493700;9783662493687

The continual increase of the integrated circuit complexity results in the more signal lines close to each other;this may produce the coupling effects among the signal lines. One of main coupling effects is crosstalk effect. In this paper, a new method is presented for the test pattern generation for the multiple victim lines of crosstalk effects;the method makes use of the binary decision diagrams (BDD). First, the BDDs of the circuit under test are built to express the circuit structure and logic values related to crosstalk effects. Second, the test patterns of crosstalk faults are produced by performing the operations on these BDDs and searching for the input assignments of the decision diagrams. The experimental results show that the method proposed in this paper can produce the test patterns of crosstalk effects in shorter time.

关键词： Digital circuits Crosstalk effects Multiple victim lines test pattern generation Binary decision diagram

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FUNCTIONAL FAULT SIMULATION AS A GUIDE FOR BIASED-RANDOM test pattern generation

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IEEE TRANSACTIONS ON COMPUTERS 1991年第1期40卷 66-79页

作者： SILBERMAN, GM SPILLINGER, I TECHNION ISRAEL INST TECHNOL DEPT ELECT ENGNIL-32000 HAIFAISRAEL

We present an approach to the generation of test patterns for implementation level faults, using fault simulation on a functional level description of a combinational VLSI design, together with an appropriate functional fault model. Our methodology uses the difference fault model (DFM), a formal abstraction of the faults at the implementation level, as the basis for fault simulation at the functional level. Incremental information from fault simulation results provides guidance for the generation of nonuniformly distributed random test patterns using a backtracing process. The quality of the generated patterns is measured in terms of their coverage of implementation faults.

关键词： BACKTRACING PROCESS BIASED-RANDOM test patternS DIFFERENCE FAULT MODEL FUNCTIONAL FAULT SIMULATION test pattern generation

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Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic test pattern generation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2019年第2期38卷 245-252页

作者： Alizadeh, Bijan Sharafinejad, Seyyed Reza Univ Tehran Sch Elect & Comp Engn Coll Engn Tehran *** Iran

As the complexity of digital designs continuously increases, existing methods to ensure their correctness are facing more serious challenges. Although many studies have been provided to enhance the efficiency of debugging methods, they are still suffering from the lack of scalable automatic correction mechanisms. In this paper, we propose a method for correcting multiple design bugs in gate level circuits. To reduce the correction time, an incremental satisfiability-based mechanism is proposed which not only does not require a complete set of test patterns to produce a gate level implementation which does not exhibit erroneous behavior, but also will not reintroduce old bugs after fixing new bugs. The results show that our method can quickly and accurately suggest corrected gates even for large industrial circuits with many bugs. Average improvements in terms of the runtime and memory usage in comparison with existing methods are 2.8x and 6.5x, respectively. Also, the results show that our method compared to the state-of-the-art methods needs 2.6x less test patterns.

关键词： Auto-correction debug satisfiability test pattern generation

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A built-in reseeding technique for LFSR-based test pattern generation

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2003年第12期E86A卷 3056-3062页

作者： Shi, Y Zhang, Z Kimura, S Yanagisawa, M Ohtsuki, T Waseda Univ Dept Elect Informat & Commun Engn Tokyo 1698555 Japan Southeast Univ Nanjing Peoples R China Waseda Univ Kitakyushu Fukuoka 8080135 Japan

Reseeding technique is proposed to improve the fault coverage in pseudo-random testing. However most of previous works on reseeding is based on storing the seeds in an external tester or in a ROM. In this paper we present a built-in reseeding technique for LFSR-based test pattern generation. The proposed structure can run both in pseudorandom mode and in reseeding mode. Besides, our method requires no storage for the seeds since in reseeding mode the seeds can be generated automatically in hardware. In this paper we also propose an efficient grouping algorithm based on simulated annealing to optimize test vector grouping. Experimental results for benchmark circuits indicate the superiority of our technique against other reseeding methods with respect to test length and area overhead. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other techniques proposed so far.

关键词： reseeding LFSR BIST test pattern generation

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Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

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IEEE TRANSACTIONS ON COMPUTERS 2000年第10期49卷 1083-1099页

作者： Psarakis, M Gizopoulos, D Paschalis, A Zorian, Y NCSR Demokritos Inst Informat & Telecommun Athens 15310 Greece Univ Piraeus Dept Informat Piraeus 18534 Greece Univ Athens Dept Informat GR-15771 Athens Greece LogicVis Inc San Jose CA 95110 USA

Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition;it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic test pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including ail practical one-dimensional ILAs, as well as a number of more complex benchmarks.

关键词： sequential fault modeling test pattern generation robust testing iterative logic arrays

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