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IEEE East-West Design and test Symposium (EWDTS)

作者： Mosin, Sergey Vladimir State Univ Dept Comp Engn Vladimir Russia

ISBN: (纸本)9781467377768

testing and diagnosis of mixed-signal integrated circuits are very important and complex tasks, which require selection the most relevant test methods for analog and digital subcircuits and subsequent their matching for comprehensive testing of a circuit on the whole. Two basic models for description the test process of mixed-signal IC based on the algebraic automata theory are proposed. The method of test program generation for mixed-signal IC in the form of automata network is presented in the paper. Generated test programs take into account the features of CUT and used test equipment and also ensure matching of applied test methods for hierarchical testing of mixed-signal IC. The method provides the feasibility to the automated test program generation for mixed-signal IC testing with various resolving ability using the state-of-the-art ATE. Experimental results of the method application for the mixed-signal circuit are presented.

关键词： test program generation mixed-signal integrated circuits design-for-testability automata network

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Automatic test program generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2013年第7期21卷 1220-1233页

作者： Zhang, Ying Li, Huawei Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China Linkoping Univ Embedded Syst Lab SE-58183 Linkoping Sweden

Software-based self-testing (SBST) has been a promising method for processor testing, but the complexity of the state-of-art processors still poses great challenges for SBST. This paper utilizes the executing trace collected during executing training programs on the processor under test to simplify mappings and functional constraint extraction for ports of inner components, which facilitate structural test generation with constraints at gate level, and automatic test instruction generation (ATIG) even for hidden control logic (HCL). In addition, for sequential HCL, we present a test routine generation technique on the basis of an extended finite state machine, so that structural patterns for combinational subcircuits in the sequential HCL can be mapped into the test routines to form a test program. Experimental results demonstrate that the proposed ATIG method can achieve good structural fault coverage with compact test programs on modern processors.

关键词： Constraint extraction instruction testing processor self-testing software-based self-testing (SBST) test program generation

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Automatic test program generation for Transition Delay Faults in Pipelined Processors 5

Automatic Test Program Generation for Transition Delay Fault...

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5th IEEE International test Conference in Asia (ITC-Asia)

作者： Chen, Kai-Hsun Yang, Bo-Yi Liang, Jia-Ruei Chen, Hung-Lin Huang, Jiun-Lang Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan Natl Taiwan Univ Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9781665413343

For processor cores, software-based self-test (SBST) is a promising complement to scan-based testing, especially for applications that demand high reliability. However, most prior SBST techniques only target stuck-at faults and thus fall short in detecting aging induced timing violations. In this paper, we propose an automatic test program generator for detection of transition delay faults (TDFs) in pipelined processors. The key technique is the conversion of scan-based launch-on-capture (LoC) TDF test patterns to instruction sequences, which are combined to form the self-test program. In the field, the processor under test can execute the test program on demand, in its functional mode, to detect TDFs. To facilitate the pattern-to-instruction conversion, a test program template is developed. Derived from the pipelined processor operation, the template helps systematically and efficiently set the flip-flop values specified in LoC test patterns. The proposed technique is validated on a MIPS32 processor and achieves 97.82% transition delay fault coverage.

关键词： software-based self-test test program generation reliability aging transition delay fault.

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MicroTESK: A Tool for Constrained Random test program generation for Microprocessors 11th

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11th International Andrei P. Ershov Informatics Conference on Perspectives of System Informatics (PSI)

作者： Kamkin, Alexander Tatarnikov, Andrei Russian Acad Sci Inst Syst Programming Moscow Russia Lomonosov Moscow State Univ Moscow Russia Moscow Inst Phys & Technol Dolgoprudnyi Moscow Region Russia Natl Res Univ Higher Sch Econ Moscow Russia

ISBN: (纸本)9783319743134;9783319743127

The paper presents MicroTESK, a tool for test program generation for functional verification of microprocessors. It generates test programs from templates which describe generation tasks in terms of constraints that must be satisfied in order to reach certain coverage goals. The tool uses formal specifications of the instruction set as a source of knowledge about the microprocessor under verification. This gives several advantages. First, the tool is easily adapted to new architectures by providing corresponding specifications. Second, constraints that constitute coverage model are automatically extracted from specifications. Third, a reference model used to track the microprocessor state during test generation is constructed on the basis of specifications. Such an approach helps to reduce the effort required to create test programs and increase the quality of testing. The tool has been successfully applied in industrial projects for verification of ARMv8 and MIPS64 microprocessors.

关键词： Microprocessors Functional verification test program generation Formal specifications Instruction set architectures

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Compiler Bug Isolation via Effective Witness test program generation 2019

Compiler Bug Isolation via Effective Witness Test Program Ge...

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27th ACM Joint Meeting on European Software Engineering Conference (ESEC) / Symposium on the Foundations of Software Engineering (FSE)

作者： Chen, Junjie Han, Jiaqi Sun, Peiyi Zhang, Lingming Hao, Dan Zhang, Lu Tianjin Univ Coll Intelligence & Comp Tianjin Peoples R China Peking Univ MoE Key Lab High Confidence Software Technol Beijing Peoples R China Univ Texas Dallas Richardson TX 75083 USA Peking Univ Beijing Peoples R China

ISBN: (纸本)9781450355728

Compiler bugs are extremely harmful, but are notoriously difficult to debug because compiler bugs usually produce few debugging information. Given a bug-triggering test program for a compiler, hundreds of compiler files are usually involved during compilation, and thus are suspect buggy files. Although there are lots of automated bug isolation techniques, they are not applicable to compilers due to the scalability or effectiveness problem. To solve this problem, in this paper, we transform the compiler bug isolation problem into a search problem, i.e., searching for a set of effective witness test programs that are able to eliminate innocent compiler files from suspects. Based on this intuition, we propose an automated compiler bug isolation technique, DiWi, which (1) proposes a heuristic-based search strategy to generate such a set of effective witness test programs via applying our designed witnessing mutation rules to the given failing test program, and (2) compares their coverage to isolate bugs following the practice of spectrum-based bug isolation. The experimental results on 90 real bugs from popular GCC and LLVM compilers show that DiWi effectively isolates 66.67%/78.89% bugs within Top-10/Top-20 compiler files, significantly outperforming state-of-the-art bug isolation techniques.

关键词： Compiler Debugging Bug Isolation test program generation

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test program generation for Mixed-Signal Integrated Circuits Based on Automata Network

Test Program Generation for Mixed-Signal Integrated Circuits...

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IEEE East-West Design & test Symposium

作者： Sergey Mosin Computer engineering department Vladimir State University (VSU) Vladimir Russia

ISBN: (纸本)9781467377775

关键词： test program generation mixed-signal integrated circuits design-for-testability automata network

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Reinforcement-Learning Based test program generation for Software-Based Self-test

Reinforcement-Learning Based Test Program Generation for Sof...

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28th IEEE Asian test Symposium (ATS)

作者： Chen, Ching-Yuan Huang, Jiun-Lang Natl Taiwan Univ Grad Inst Elect Engn Taipei Taiwan Natl Taiwan Univ Dept Elect Engn Taipei Taiwan

ISBN: (纸本)9781728126951

Software-based Self-test (SBST) has been recognized as a promising complement to scan-based structural Built-in Self-test (BIST), especially for in-field self-test applications. In response to the ever-increasing complexities of the modern CPU designs, machine learning algorithms have been proposed to extract processor behavior from simulation data and help constrain ATPG to generate functionally-compatible patterns. However, these simulation-based approaches in general suffer sample inefficiency, i.e., only a small portion of the simulation traces are relevant to fault detection. Inspired by the recent advances in reinforcement learning (RL), we propose an RL-based test program generation technique for transition delay fault (TDF) detection. During the training process, knowledge learned from the simulation data is employed to tune the simulation policy;this close-loop approach significantly improves data efficiency, compared to previous open-loop approaches. Furthermore, RL is capable of dealing with delayed responses, which is common when executing processor instructions. Using the trained RL model, instruction sequences that bring the processor to the fault-sensitizing states, i.e., TDF test patterns, can be generated. The proposed test program generation technique is applied to a MIPS32 processor. For TDF, the fault coverage is 94.94%, which is just 2.57% less than the full-scan based approach.

关键词： Software-based self-test reinforcement learning test program generation stimuli generator constraint extraction

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Compiler test-program generation via Memoized Configuration Search 23

Compiler Test-Program Generation via Memoized Configuration ...

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45th IEEE/ACM International Conference on Software Engineering (ICSE)

作者： Chen, Junjie Suo, Chenyao Jiang, Jiajun Chen, Peiqi Li, Xingjian Tianjin Univ Coll Intelligence & Comp Tianjin Peoples R China

ISBN: (纸本)9781665457019

To ensure compilers' quality, compiler testing has received more and more attention, and test-program generation is the core task. In recent years, some approaches have been proposed to explore test configurations for generating more effective test programs, but they either are restricted by historical bugs or suffer from the cost-effectiveness issue. Here, we propose a novel test-program generation approach (called MCS) to further improving the performance of compiler testing. MCS conducts memoized search via multi-agent reinforcement learning (RL) for guiding the construction of effective test configurations based on the memoization for the explored test configurations during the on-the-fly compiler-testing process. During the process, the elaborate coordination among configuration options can be also well learned by multi-agent RL, which is required for generating bug-triggering test programs. Specifically, MCS considers the diversity among test configurations to efficiently explore the input space and the testing results under each explored configuration to learn which portions of space are more bug-triggering. Our extensive experiments on GCC and LLVM demonstrate the performance of MCS, significantly outperforming the state-of-the-art test-program generation approaches in bug detection. Also, MCS detects 16 new bugs on the latest trunk revisions of GCC and LLVM, and all of them have been confirmed or fixed by developers. MCS has been deployed by a global IT company (i.e., Huawei) for testing their in-house compiler, and detects 10 new bugs (covering all the 5 bugs detected by the compared approaches), all of which have been confirmed.

关键词： Compiler testing test program generation Reinforcement Learning Configuration

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Detecting Compiler Error Recovery Defects via program Mutation Exploration

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2025年第2期51卷 389-412页

作者： Tang, Yixuan Zhang, Jingxuan Li, Xiaochen Huang, Zhiqiu Jiang, He Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing 211106 Peoples R China Dalian Univ Technol DUT Sch Software Dalian 116600 Peoples R China Minist Ind & Informat Technol Key Lab Safety Crit Software Dev & Verificat Nanjing 211106 Peoples R China Collaborat Innovat Ctr Novel Software Technol & In Nanjing 211106 Peoples R China

Compiler error recovery diagnostics facilitates software development as it provides the possible causes and suggestions on potential programming errors. However, due to compiler bugs, error recovery diagnostics could be erroneous, spurious, missing, or even crashing for mature production compilers like GCC and Clang. Compiler testing is one of the most widely used ways of ensuring its quality. However, existing compiler diagnostics testing approaches (e.g., DIPROM) only consider the typically syntactically valid test programs as inputs, which are unlikely to trigger compiler error recovery defects. Therefore, in this paper, we propose the first mutation based approach for Compiler Error Recovery diagnostics testing, called CERtest. Specifically, CERtest first explores the mutation space for a given seed program, and leverages a series of mutation configurations (which are referred as a series of mutators applying for a seed) to iteratively mutate the structures of the seed, so as to generate error-sensitive program variants for triggering compiler error recovery mechanisms. To effectively construct error-sensitive structures, CERtest then applies a novel furthest-first based selection approach to select a set of representative mutation configurations to generate program variants in each iteration. With the generated program variants, CERtest finally leverages differential testing to detect error recovery defects in different compilers. The experiments on GCC and Clang demonstrate that CERtest outperforms five state-of-the-art approaches (i.e., DIPROM, Ccoft, Clang-fuzzer, AFL++, and HiCOND) by up to 13.10%similar to 221.61% on average in the term of bug-finding capability, and CERtest detects 9 new error recovery defects, 5 of which have been confirmed or fixed by developers.

关键词： program processors Codes testing programming Periodic structures Software development management Software Java Internet Computer languages Compiler testing test program generation program mutation differential testing

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On the Automatic generation of Optimized Software-Based Self-test programs for VLIW Processors

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第4期22卷 813-823页

作者： Sabena, Davide Reorda, Matteo Sonza Sterpone, Luca Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

Very long instruction word (VLIW) processors are increasingly employed in a large range of embedded signal processing applications, mainly due to their ability to provide high performances with reduced clock rate and power consumption. At the same time, there is an increasing request for efficient and optimal test techniques able to detect permanent faults in VLIW processors. Software-based self-test (SBST) methods are a consolidated and effective solution to detect faults in a processor both at the end of the production phase or during the operational life;however, when traditional SBST techniques are applied to VLIW processors, they may prove to be ineffective (especially in terms of size and duration), due to their inability to exploit the parallelism intrinsic in these architectures. In this paper, we present a new method for the automatic generation of efficient test programs specifically oriented to VLIW processors. The method starts from existing test programs based on generic SBST algorithms and automatically generates effective test programs able to reach the same fault coverage, while minimizing the test duration and the test code size. The method consists of four parametric phases and can deal with different VLIW processor models. The main goal of the paper is to show that in the case of VLIW processors, it is possible to automatically generate an effective test program able to achieve high fault coverage with minimal test time and required resources. Experimental data gathered on a case study demonstrate the effectiveness of the proposed approach;results show that this method is able to exploit the intrinsic parallelism of the VLIW processor, taming the growth in size, and duration of the test program when the processor size grows.

关键词： Software-based self-test (SBST) test program generation very long instruction word (VLIW) processors

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