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IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Jasnetski, Artjom Raik, Jaan Tsertov, Anton Ubar, Raimund Teston Lab OU Tallinn Estonia Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781479967803

The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called "unintended actions", is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.

关键词： microprocessor software-based self-test (SBST) test program generation high-level decision diagrams

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BPGen: Functional Verification of Branch Misprediction Recovery Logic via ADL

BPGen: Functional Verification of Branch Misprediction Recov...

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IEEE International Conference on Communication Problem-Solving (ICCP)

作者： Yang, An Beijing Informat Sci & Technol Univ Informat & Network Management Ctr Beijing Peoples R China

ISBN: (纸本)9781467365444

Branch misprediction logic is very important in microprocessor control logic design. This paper presents a method for functional verification of branch misprediction recovery logic, named BPGen, which uses ADL (architecture description language) to describe the system architecture of microprocessor, defines fault model and instruction classification for branch misprediction logic, and generates the test programs automatically. The experiment result showed that the BPGen tool could complete the branch misprediction verification within an acceptable time, detected all the 23 bugs in an actual design project, and detected all the 38 design errors generated by the popular mutation technology.

关键词： Pipelined processor functional verification fault coverage test program generation branch misprediction

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New Fault Models and Self-test generation for Microprocessors using High-Level Decision Diagrams

New Fault Models and Self-Test Generation for Microprocessor...

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IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

作者： Artjom Jasnetski Jaan Raik Anton Tsertov Raimund Ubar Testonica Lab OU Department of Computer Engineering Tallinn University of Technology

ISBN: (纸本)9781479967810

关键词： Microprocessor Software-based self-test (SBST) test program generation High-level decision diagrams

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BPGen: Functional Verification of Branch Misprediction Recovery Logic via ADL

BPGen: Functional Verification of Branch Misprediction Recov...

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2015 International Conference on Communication Problem-Solving(ICCP)

作者： An Yang Information & Network Management Center Beijing Information Science & Technology University

Branch misprediction logic is very important in microprocessor control logic design. This paper presents a method for functional verification of branch misprediction recovery logic, named BPGen, which uses ADL(architecture description language) to describe the system architecture of microprocessor, defines fault model and instruction classification for branch misprediction logic, and generates the test programs automatically. The experiment result showed that the BPGen tool could complete the branch misprediction verification within an acceptable time, detected all the 23 bugs in an actual design project, and detected all the 38 design errors generated by the popular mutation technology.

关键词： Pipelined processor functional verification fault coverage test program generation branch misprediction

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On the Automatic generation of Optimized Software-Based Self-test programs for VLIW Processors

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第4期22卷 813-823页

作者： Sabena, Davide Reorda, Matteo Sonza Sterpone, Luca Politecn Torino Dipartimento Automat & Informat I-10129 Turin Italy

Very long instruction word (VLIW) processors are increasingly employed in a large range of embedded signal processing applications, mainly due to their ability to provide high performances with reduced clock rate and power consumption. At the same time, there is an increasing request for efficient and optimal test techniques able to detect permanent faults in VLIW processors. Software-based self-test (SBST) methods are a consolidated and effective solution to detect faults in a processor both at the end of the production phase or during the operational life;however, when traditional SBST techniques are applied to VLIW processors, they may prove to be ineffective (especially in terms of size and duration), due to their inability to exploit the parallelism intrinsic in these architectures. In this paper, we present a new method for the automatic generation of efficient test programs specifically oriented to VLIW processors. The method starts from existing test programs based on generic SBST algorithms and automatically generates effective test programs able to reach the same fault coverage, while minimizing the test duration and the test code size. The method consists of four parametric phases and can deal with different VLIW processor models. The main goal of the paper is to show that in the case of VLIW processors, it is possible to automatically generate an effective test program able to achieve high fault coverage with minimal test time and required resources. Experimental data gathered on a case study demonstrate the effectiveness of the proposed approach;results show that this method is able to exploit the intrinsic parallelism of the VLIW processor, taming the growth in size, and duration of the test program when the processor size grows.

关键词： Software-based self-test (SBST) test program generation very long instruction word (VLIW) processors

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Software-based self-test generation for microprocessors with high-level decision diagrams

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PROCEEDINGS OF THE ESTONIAN ACADEMY OF SCIENCES 2014年第1期63卷 48-61页

作者： Jasnetski, Artjom Ubar, Raimund Tsertov, Anton Brik, Marina Tallinn Univ Technol Dept Comp Engn EE-12618 Tallinn Estonia

This paper presents a novel approach to automated behavioural level test program generation for microprocessors using the model of high-level decision diagrams (HLDD) for representing instruction sets. The methodology of using HLDDs for modelling of microprocessors, and a new HLDD-based fault model are developed. The procedures for automated test program generation are presented using a formal model of HLDDs. The feasibility and efficiency of the new methodology are demonstrated by carrying out experimental research on test generation for a 8-bit microprocessor. The results are promising, showing the advantages of the new method and demonstrating better quality of tests compared to previous results.

关键词： microprocessor software-based self-test test program generation high-level decision diagrams.

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Software-based Self-test generation for Microprocessors with High-Level Decision Diagrams

Software-based Self-Test Generation for Microprocessors with...

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15th Latin American test Workshop (LATW)

作者： Ubar, Raimund Tsertov, Anton Jasnetski, Artjom Brik, Marina Tallinn Univ Technol Dept Comp Engn EE-19086 Tallinn Estonia

ISBN: (纸本)9781479947119

Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research community for the last decades. Generally, the inextinguishable attention to this method is mainly caused by continuous growth of complexity of modern processors that poses new research challenges. One of these challenges is automated generation of software-based self-tests. Through the years the main research trend was focused on reducing the processor representation complexity by shifting the modeling process towards more general abstraction layers. This paper presents the approach for high-level processor modeling, which is the next convolution of SBST methodology. We propose the methodology for processor modeling at behavioral level that can be used for automatic generation of SBST programs. The method leads to significant complexity reduction compared to RT-level and as experimental results show the efficiency of SBST in terms of fault coverage is not compromised in comparison to state-of-the-art SBST approaches.

关键词： microprocessor software-based self-test (SBST) test program generation high-level decision diagrams

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On the optimized generation of Software-Based Self-test programs for VLIW processors 20

On the optimized generation of Software-Based Self-Test prog...

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20th IFIP/IEEE International conference on Very Large Scale Integration (VLSI-SoC)

作者： Sabena, D. Reorda, M. Sonza Sterpone, L. Politecn Torino Dipartimento Automat & Informat Turin Italy

ISBN: (纸本)9781467326582

Software-Based Self-test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this paper we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while reducing the test duration and the test code size. The method consists of three parametric phases and can deal with different VLIW processor models. The main goal of the proposed method is to automatically obtain a test program able to effectively reduce the test time and the required resources. Experimental results gathered on a case study show the effectiveness of the proposed approach.

关键词： SBST VLIW test program generation

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Automatic test Wrapper Synthesis for a Wireless ATE Platform

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IEEE DESIGN & test OF COMPUTERS 2010年第3期27卷 31-41页

作者： Yang, Chun-Yu Chen, Ying-Yen Chen, Sung-Yu Liou, Jing-Jia Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

To ensure reliable test data communication in a wireless test system, information can be encapsulated in packets equipped with error correction and retransmission capability. Systems employing such an approach require a complex test interface (test wrapper) to bridge communication and test modules. This article proposes a modular test wrapper design and an automation tool to create a wrapper for a target circuit under test and associated test program.

关键词： Design And test test program generation test Wrapper Synthesis Core test Language Wireless test System

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Software-based self-test of processors under power constraints

Software-based self-test of processors under power constrain...

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Design, Automation and test in Europe Conference and Exhibition (DATE 06)

作者： Zhou, Jun Wunderlich, Hans-Joachim Univ Stuttgart Inst Comp Architecture & Comp Engn D-70569 Stuttgart Germany

ISBN: (纸本)9783981080117

Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initialization tests for the whole system. In this paper for the first time a structural SBST methodology is proposed which optimizes energy average power consumption, test length and fault coverage at the same time.

关键词： test program generation processor test low power test

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