In this paper,we presented algorithms for testing gain error,offset error,differential nonlinearity(DNL) and integral nonlinearity(INL)of analog-to-digital converters(ADC),and proposed an easily integrated built-in se...
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In this paper,we presented algorithms for testing gain error,offset error,differential nonlinearity(DNL) and integral nonlinearity(INL)of analog-to-digital converters(ADC),and proposed an easily integrated built-in self-test(BIST)scheme on chip,which has been designed using Chartered 0.35μm *** experimental results show that the proposed BIST scheme has low area overhead,low test cost and high test accuracy.
(I)n this paper, we presented algorithms for testing gain error. offset error. differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC). and proposed an easily integrated b...
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(纸本)078037889X
(I)n this paper, we presented algorithms for testing gain error. offset error. differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC). and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using TSMC 0.25mum technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.
Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of th...
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Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.
A new stability test algorithm for two-dimensional (2-D) digital filters is proposed, which uses the inner term polynomials of the corresponding 2-D test polynomial to construct a test table in order to simplify the s...
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A new stability test algorithm for two-dimensional (2-D) digital filters is proposed, which uses the inner term polynomials of the corresponding 2-D test polynomial to construct a test table in order to simplify the stability test procedure. Different from other well-known table test algorithms, the new test algorithm can directly use the one-dimensional (1-D) Schur procedure to test the zeros' distribution of a 2-D complex polynomial in the unit bidisk.
A design for testability technique and an associated test algorithm are presented for CMOS combinational circuits. It will be shown that stuck-open faults, stuck-on faults, bridging faults and delay faults can all be ...
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A design for testability technique and an associated test algorithm are presented for CMOS combinational circuits. It will be shown that stuck-open faults, stuck-on faults, bridging faults and delay faults can all be detected in CMOS combinational circuits using such test procedure.
A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small te...
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A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small test time can be achieved.
This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high faul...
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This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A fault oriented test generation algorithm combined with a heuristic test generation algorithm are the essential ingredients of this package. The heuristic algorithm generates an initial set of test vectors which is verified against a predefined list of possible faults. A fault oriented algorithm is then used to generate test vectors that can detect faults not detected by this set. The fault oriented algorithm uses a modified D -algorithm which includes look ahead features and a new seven valued logic to improve the average speed of the test generation process. Fault coverages in the 90% range were obtained using the test vectors generated by this package. test vectors generated by both algorithms can optionally be stitched into sequences in a way that does not compromise their fault coverage. This reduces the overhead in actual test application time by cutting down the number of the serial scan in/out operations.
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