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检索条件"主题词=Test algorithm"
37 条 记 录,以下是31-40 订阅
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A complete BIST scheme for ADC linearity testing
A complete BIST scheme for ADC linearity testing
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2004 7th International Conference on Solid-State and Integrated Circuits Technology(ICSICT 2004)
作者: Wu Guanglin Ling Ming Rao Jin Shi Longxing (National ASIC System Engineering Center, Southeast University, Nanjing 210096, China)
In this paper,we presented algorithms for testing gain error,offset error,differential nonlinearity(DNL) and integral nonlinearity(INL)of analog-to-digital converters(ADC),and proposed an easily integrated built-in se... 详细信息
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Implementation of a BIST scheme for ADC test  5
Implementation of a BIST scheme for ADC test
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5th International Conference on ASIC
作者: Wu, GL Rao, J Ren, AL Ling, M Southeast Univ Natl ASIC Syst Engn Ctr Nanjing 210096 Peoples R China
(I)n this paper, we presented algorithms for testing gain error. offset error. differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC). and proposed an easily integrated b... 详细信息
来源: 评论
Efficient path delay testing using scan justification
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ETRI JOURNAL 2003年 第3期25卷 187-194页
作者: Huh, KH Kang, YS Kang, S LG Elect Seoul South Korea Yonsei Univ Seoul 120749 South Korea
Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of th... 详细信息
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New stability test algorithm for two-dimensional digital filters
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 1998年 第7期45卷 739-741页
作者: Yang, X Unbehauen, R No Jiao Tong Univ Inst Informat Sci Beijing 100044 Peoples R China Univ Erlangen Nurnberg Lehrstuhl Allgemeine & Theoret Elektrotech D-91058 Erlangen Germany
A new stability test algorithm for two-dimensional (2-D) digital filters is proposed, which uses the inner term polynomials of the corresponding 2-D test polynomial to construct a test table in order to simplify the s... 详细信息
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FAULT-DETECTION IN TFCMOS DFCMOS COMBINATIONAL GATES
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INTEGRATION-THE VLSI JOURNAL 1993年 第2期15卷 201-227页
作者: BUONANNO, G LOMBARDI, F SCIUTO, D SHEN, YN TEXAS A&M UNIV SYST DEPT COMP SCICOLL STNTX 77843
A design for testability technique and an associated test algorithm are presented for CMOS combinational circuits. It will be shown that stuck-open faults, stuck-on faults, bridging faults and delay faults can all be ... 详细信息
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NEW algorithm FOR testING RANDOM-ACCESS MEMORIES
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ELECTRONICS LETTERS 1991年 第7期27卷 574-575页
作者: RAJSUMAN, R Dept. of Comput. Eng. & Sci. Case Western Reserve Univ. Cleveland OH USA
A linear time complexity algorithm to test RAMs is presented. The algorithm requires only 7n read/write operations and provides an extensive fault coverage. The main advantage of the proposed scheme is that a small te... 详细信息
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test-GENERATION AND FAULT-DETECTION FOR VLSI PPL CIRCUITS
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INTEGRATION-THE VLSI JOURNAL 1989年 第3期7卷 303-324页
作者: AMIN, AAM SMITH, KF Department of Computer Science The University of Utah Salt Lake City UT 84112 U.S.A.
This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high faul... 详细信息
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