检索结果-内蒙古大学图书馆

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Jiao, Yuzhong Li, Yiu Kei Chan, Chi Hong Li, Yun Ai, Zhilin Simbury Ltd Hong Kong Peoples R China

ISBN: (纸本)9781665450737

For keyword spotting (KWS) systems that usually work in mobile devices, a low-complexity design is essential for long stand-by time. Audio feature extraction and classifier modeling are the two main components of KWS systems. Log Mel- Frequency Spectral Coefficient (MFSC) is common for audio feature extraction due to its low complexity and good performance. Binary neural network (BNN) classifier, which owns binary weights and activations and performs convolution with XNOR, is applicable to low-complexity KWS applications. However, audio features are usually quantized with multiple-bit binary code to maintain high classification accuracy, which requires addition (ADD) operations in the first convolutional layer of the BNN model. Therefore, both XNOR and ADD units are needed in the BNN accelerator. To further reduce the complexity of KWS systems, we propose a new feature extraction method: thermometer codes of MFSC (MFSC-TC). Without LOG and DELTA operations, it is simpler than other MFSC-based methods. More importantly, convolution of all layers can be done by XNOR units due to the feature of thermometer code. The experiments with the Google Speech Commands dataset validate that the MFSC-TC-based BNN models outperform the models with more layers using other feature extraction methods.

关键词： keyword spotting binary neural network feature extraction thermometer code

来源：评论

学校读者我要写书评

暂无评论

Design of thermometer code-to-gray code converter circuit in quantum-dot cellular automata for nano-computing network

引用

PHOTONIC NETWORK COMMUNICATIONS 2021年第3期41卷 259-273页

作者： Das, Jadav Chandra De, Debashis Maulana Abul Kalam Azad Univ Technol WB Dept Informat Technol Haringhata 741249 W Bengal India Maulana Abul Kalam Azad Univ Technol WB Dept Comp Sci & Engn Haringhata 741249 W Bengal India Univ Western Australia Dept Phys Crawley WA 6009 Australia

This article proposes the thermometer code converter, which eliminates the requirement of binary code converter to generate gray codes in different digital modulation techniques like pulse code modulation. The nanoscale faster low-power circuit for these thermometer code-to-gray code converter has been achieved with quantum-dot cellular automata (QCA). The proposed converter circuit is made up with new QCA 2:1 multiplexer, which dominates the other existing designs in terms of QCA cells and device density. The circuits are evaluated based on area and operating speed. The design consistency is verified through theoretical values. The dissipated energy explores that the designs have lower energy dissipation. Stuck-at-fault effect analysis on the circuits has been performed. Besides, defect analysis caused by single missing cells, single extra added cells and misplaced cells is also explored. Test vectors are proposed to achieve 100% defect coverage. As encoders, these circuits can be widely employed in those high-performance functions that impose extraordinary design constraints with respect to high frequency, minimal area and low energy consumption.

关键词： thermometer code Gray code QCA Multiplexer Energy dissipation

来源：评论

学校读者我要写书评

暂无评论

Area-Efficient QC-LDPC Decoding Architecture With thermometer code-Based Sorting and Relative Quasi-Cyclic Shifting

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第6期71卷 2897-2910页

作者： Jang, Boseon Jang, Hyejung Kim, Sungho Choi, Kangjoon Park, In-Cheol Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea

The 5G New-Radio (NR) communication standard requires high throughput and low latency, so low-density parity-check (LDPC) codes, which have higher inherent parallelism and lower decoding complexity than turbo codes, were adopted as the main coding method for data channels. In traditional LDPC min-sum decoders, the check node unit was realized using a sorting unit based on the min-tree structure. However, this structure resulted in high hardware complexity and long latency. To address this issue, we propose a new sorting method based on the thermometer code-based number system. Additionally, we introduce a new LDPC decoding architecture that reduces the number of QSN stages from two to one, significantly lowering the shifting logic complexity needed to support different lifting sizes. This is achieved by using relative shift amounts instead of absolute shift amounts specified in the parity check matrix. The proposed decoder implemented using a partially parallel structure in a 65nm CMOS technology satisfies the various operation modes and the throughput requirements of the 5G NR standard, and boasts a higher normalized throughput than state-of-the-art LDPC decoders.

关键词： Low-density parity-check codes thermometer code normalized min-sum algorithm VLSI hardware implementation 5G new-radio standard area-efficient quasi-cyclic LDPC decoder

来源：评论

学校读者我要写书评

暂无评论

Design of Novel Multiplexer Based thermometer to Binary code Encoder for 4 Bit Flash ADC 2

Design of Novel Multiplexer Based Thermometer to Binary Code...

引用

2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT)

作者： Mayur, S. Marinaik New Horizon Coll Engn Bengaluru India

ISBN: (纸本)9781509037049

In this paper, a novel multiplexer based thermometer to binary code Encoder For 4 Bit Flash ADC is proposed. The proposed encoder design uses 2:1 multiplexes (MUX) and 2 input XOR gates for converting thermometer code to binary code. Initially 2:1 MUX are used to convert the thermometer code to equivalent gray code. The resulting gray code is then converted to the binary code using XOR gates. Low power consumption is achieved in the proposed design with the grounding concept and avoiding the additional inverters compared to the conventional encoder design. The proposed encoder is implemented in 180 nm CMOS, N-well technology with 1.8 V supply voltage and was simulated using Cadence Spectre simulator. Simulation results shows reduction in power up to 60% when compared with conventional encoder architectures. The proposed design has a figure-of-merit (FOM) of 13.28 fJ with the propagation delay of 0.5180 ns.

关键词： Analog to digital converters self-re-configurable property figure of merit thermometer code gray code

来源：评论

学校读者我要写书评

暂无评论

Energy-efficient high-linearity SAR ADC with a unary-binary hybrid capacitor switching method

引用

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2025年 190卷

作者： Xu, Guangjian Zhang, Chang Li, Qinqin Tong, Xingyuan Xian Univ Posts & Telecommun Sch Elect Engn Xian 710121 Peoples R China

This study developed a 10-bit 10 MS/s energy-efficient and high-linearity successive approximation register (SAR) analog-to-digital converter (ADC). The design utilized a capacitor array structure employing ''3-bit thermometer code + 6-bit binary code'' to achieve 10-bit quantization through a V-cm-based three-level capacitor switching scheme. The thermometer codes optimized the switching capacitors of the most significant bits to enhance linearity. Further, a unary and binary code control method was implemented to automatically switch across the remaining unary code capacitors when the differential output of the digital-to-analog converter was below 64 least significant bits (LSB). This method reduces the switching energy by 30% compared to the binary CDAC, while RMSDNL and RMSINL are reduced by 47.50% and 26.08%, respectively. The 10-bit SAR ADC was designed with 0.18 mu m CMOS technology, and the ADC core occupied an area of 0.077 mm(2). At supply and reference voltages of 1.2 V, the ADC achieved differential non-linearity and integral non-linearity values of +0.36/- 0.32 and +0.4/- 0.37 LSB, respectively, at a sampling frequency of 10 MS/s and with a 1% capacitor mismatch. At an input signal frequency of 4.65 MHz, the ADC achieved a signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 60.07 and 80.03 dB, respectively. The ADC consumed a power of 137.36 mu W, and the Walden figure of merit was 16.74 fJ/conversion-step.

关键词： thermometer code Linearity Energy-efficient Analog-to-digital converter (ADC)

来源：评论

学校读者我要写书评

暂无评论

Sum of Products: Computation using Modular thermometer codes

Sum of Products: Computation using Modular Thermometer Codes

引用

International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Vun, C. H. Premkumar, A. B. Zhang, W. Nanyang Technol Univ Singapore Singapore Univ Malaya Dept Elect Engn Kuala Lumpur Malaysia Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781479961207

This paper presents a method for computing inner products based on the distributed arithmetic principles and thermometer codes. The input is represented in the residue domain using thermometer codes while the output is encoded in the one-hot code format. Compared to the conventional methods of evaluating inner products using binary format, the proposed system provides an elegant way of performing the modular inner products computation due to the absence of the 2(n) modulo operation encountered in binary based methods. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format with no carry propagation involved in the addition.

关键词： Distributed arithmetic inner product one-hot code residue number systems thermometer code

来源：评论

学校读者我要写书评

暂无评论

A 6-bit 4MS/s 26fJ/conversion-step segmented SAR ADC with reduced switching energy for BLE

引用

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2018年第3期46卷 375-383页

作者： Rikan, Behnam Samadpoor Abbasizadeh, Hamed Cho, Sung-Hun Kim, Sang-Yun Ali, Imran Kim, SungJin Lee, DongSoo Pu, YoungGun Lee, MinJae Hwang, KeumCheol Yang, Youngoo Lee, Kang-Yoon Sungkyunkwan Univ Coll Informat & Commun Engn Suwon South Korea Gwangju Inst Sci & Technol Sch Informat & Commun Gwangju South Korea

This paper presents a 6-bit 4MS/s segmented successive approximation register analog-to-digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital-to-analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power-hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to high and the other one to low. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog-to-digital converter is fabricated and measured in a 55-nm (shrinked 65nm) complementary metal-oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03dB, respectively. The current consumption is 4.8A from a 1.0-V supply, which corresponds to the figure of merit of 26fJ/conversion-step. The total active area of the analog-to-digital converters for the I and Q paths of the receiver is 105 mu mx140 mu m.

关键词： ADC segmented DAC splitting capacitor successive approximation thermometer code

来源：评论

学校读者我要写书评

暂无评论

A New RNS based DA Approach for Inner Product Computation

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2013年第8期60卷 2139-2152页

作者： Vun, Chan Hua Premkumar, Annamalai Benjamin Zhang, Wei Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2 modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme.

关键词： Distributed arithmetic inner product one-hot code residue number systems thermometer code

来源：评论

学校读者我要写书评

暂无评论

In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric code

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2022年第10期30卷 1473-1483页

作者： Saragada, Prasanna Kumar Das, Bishnu Prasad IIT Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttarakhand India

The article presents an efficient static random access memory (SRAM)-based in-memory computation (IMC) architecture which is capable of performing image classification with improved linearity. In this work, we proposed a thermometric code-based IMC (TC-IMC) to perform multibit multiply-and-accumulate (MAC) operations with improved linearity. An input sparsity-aware compact thermometric code approach is proposed to reduce the number of SRAM bitcells compared to the thermometric code-based encoding without loss of accuracy in the MAC operation. We proposed an optimal sampling time to improve the linearity of the TC-IMC MAC operation with maximum signal margin (SM) based on the detailed nonlinearity analysis of 8T SRAM-based TC-IMC architecture. The test chip measurement results in 180 nm process show that the proposed TC-IMC has 72% better linearity than the traditional IMC. The measured results on 100 Modified National Institute of Standards and Technology (MNIST) and CIFAR-10 test images show an accuracy of 97% and 87%, respectively. In addition, the proposed TC-IMC architecture achieves MAC compute latency of 25 ns, GOPS/kb (normalized to 1 b x 1 b) of 29.8, and energy efficiency of 2.3 TOPS/W. The simulation result of the entire 10 000 MNIST and CIFAR-10 images considering process variation effects shows an accuracy of 98.7% and 90.4%, respectively.

关键词： In-memory computation (IMC) integral nonlinearity (INL) machine learning (ML) classifier process variation sparsity-aware design static random access memories (SRAMs) thermometer code

来源：评论

学校读者我要写书评

暂无评论

A low-power,area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

引用

Science China(Information Sciences) 2014年第12期57卷 176-183页

作者： CHEN HongMing MA Song WANG Liu ZHANG Hao PAN KenYi CHENG YuHua Shanghai Research Institute of Microelectronics (SHRIME) Peking University School of Electronics Engineering and Computer Science Peking University

A new low-power,area efficiency all-digital delay-locked loop(ADDLL)circuit is proposed for *** ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz(DDR3-667/800/1066/1600)by using Phase Detector(PD),Delay Control Delay Line(DCDL),Digital Loop Filter Controller(DLFC)and Delay Generator(DG).To achieve 1.6 Gb/s/pin operation,a novel DCDL scheme is *** DCDL has a small delay with a shunt capacitor based digitally controlled delay element.A splitcontrol thermometer-code generator generates the control voltages used to set a current in the current-starved *** testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps–1.6 *** results that show the power consumption is 1.87 m W at 1.1 V with active area is 0.0137mm2.

关键词： all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：