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IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

作者： Cao, Qiankai Chen, Xi Gu, Jie Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

ISBN: (纸本)9798350311754

Tropical algebra solves complex problems with only sum and min/max operations replacing expensive multiplication and addition in linear algebra. Due to the low computing cost, tropical algebra has recently gained significant attention in a broad range of areas such as combinatorial optimization, scheduling, machine learning, etc. In this paper, we propose a generic hardware accelerator architecture for tropical algebra supporting a wide range of applications. Novel time-domain (TD) computing accelerators with special mapping, precision expansion and, unrolling techniques are proposed to further improve hardware efficiency. Test results on various tropical calculations including linear regression, dynamic programming, and neural network are shown to demonstrate an energy saving from 1.5X to 2.1X, latency saving from 2.6X to 5.2X, or an overall energy-delay-product (EDP) improvement from 3.9X-10.5X compared with conventional digital implementation manifesting the promise of the algebraic solution on low power edge devices.

关键词： tropical algebra shortest path problems dynamic programming time-domain computing

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A Low Power time-domain computing-In-Memory Micro for Binary Neural Networks

A Low Power Time-Domain Computing-In-Memory Micro for Binary...

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作者： He, Yixuan Northeastern University

学位级别：Ph.D., Doctor of Philosophy

In order to enable hardware to match complex deep learning algorithms, binary neural networks are developed and considered as hardware-friendly deep learning algorithms due to the fact that it can achieve similar inference accuracy with fewer computing resources compared with traditional convolutional neural networks. As for its VLSI implementations, the computing-in-memory (CIM) technology has been proved to solve the memory-wall bottleneck problem shown in traditional von Neumann machine and can be a perfect choice to implement neural networks with binary data. Therefore, this work proposes two novel computing-in-memory cores that implement XNOR-and-accumulate of binary neural networks with all-digital elements. Both designs use 8T-SRAM cells to perform XNOR operations inside memory array, but they accumulate the related XNOR output values in diverse ways. The time-domain CIM micro does accumulation in time domain with specialized racing structures and delay lines, whereas the all-digital micro uses low-power pathfinding counters in pure digital domain. The circuits are built and simulated in Cadence using Samsung 65nm CMOS technology with 1V power supply. The results show correct functionality and lower power consumption compared to other existing micros. The time-domain micro achieves 2730 GOPS throughput and 431.7 TOPS/W power efficiency. And the all-digital micro has 1638 GOPS throughput and 537.6 TOPS/W power efficiency. With further exploration, the proposed time-domain and all-digital pathfinding approaches can become new favorites in the field of in-memory-computing for deep learning because they have their own advantages in terms of throughput, power efficiency compared to mixed-signal approaches and traditional digital methods.

关键词： Binary neural networks computing-in-memory Low power VLSI time-domain computing Deep learning

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TDPRO: time-domain-Based computing-in Memory Engine for Ultra-Low Power ECG Processor

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第10期70卷 3908-3919页

作者： Chang, Liang Yang, Siqi Chang, Zhiyuan Fan, Haodong Zhou, Junlu Zhou, Jun Univ Elect Sci & Technol China Sch Informat & Commun Engn Chengdu 611731 Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China

For the wearable biomedical signal detection, both high accuracy and low-power consumption are critical requirements. Various works have employed the neural network to improve the detecting accuracy and develop the biomedical processor. However, the biomedical processor with neural network engine contains massive data movements and large data buffers. One solution is the computing-in memory (CIM) architecture, which locates more data near the computing engine to reduce data movements. In traditional CIM-based solution, the detecting accuracy and power consumption is difficult to be optimized simultaneously, where the accuracy should be satisfied for the detection. To date, the time-domain computing engine have been developed to employ both digital and time domain computation. In this work, we present a high-precision time-domain engine to perform 8-bit multiplication and addition operation for the biomedical signal detection. With the high precision time-domain engine, we develop a CIM-based neural-network processor, namely TDPRO, to perform the detection of arrhythmia. In addition, we develop TD-zero-jumping (TDJ) and idle-shutdown (ISD) techniques according to signal features and data mapping strategy, further optimizing the power consumption. Based on our evaluation, the TD-based 8-bit mulitply-accumulation operation is robust, without declining the accuracy of biomedical signal detection. We design a ECG processor with the proposed TDPRO architecture, which obtains 98.60% high accuracy and 75.7% power saving compared to the recent the state-of-the-art study.

关键词： time-domain computing computing-in memory ECG detection low power processor

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time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory computing 36

Time-domain Subtractive Readout Scheme for Scalable Capaciti...

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36th IEEE International System-on-Chip Conference (SOCC)

作者： Oshio, Reon Kuwahara, Takumi Kimura, Mutsumi Nakashima, Yasuhiko Nara Inst Sci & Technol NAIST Ikoma Nara Japan Ryukoku Univ Otsu Shiga Japan

ISBN: (纸本)9798350300116

In-memory computing is a promising architecture to meet the exploding demand for data-intensive workloads, including deep neural networks. In particular, analog in-memory computings (AIMCs) is a promising way to build matrix multiplication accelerators that take full advantage of data parallelism and reusability. However, most AIMCs use voltage readout circuits that have no benefit from CMOS scaling, which is an obstacle to improving computational density. We propose a method that combines capacitive AIMC and readout with near-memory time-subtraction, which is theoretically scalable concerning miniaturization and row/column parallelism and is adjustable with output resolution. We have evaluated the signed multi-bit dot product operation in post-layout simulation using circuits designed with a 180-nm process. Even with x 16 increase in row-parallelism (9 to 144), the time resolution required for readout was successfully reduced to a variation of 0.39%.

关键词： Analog In-memory computing Capacitive In-Memory computing time-domain computing

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Discrete Steps towards Approximate computing 23

Discrete Steps towards Approximate Computing

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23rd International Symposium on Quality Electronic Design (ISQED)

作者： Gansen, Michael Lou, Jie Freye, Florian Gemmeke, Tobias Merchant, Farhad Zeyer, Albert Zeineldeen, Mohammad Schlueter, Ralf Fan, Xin Rhein Westfal TH Aachen IDS Aachen Germany Rhein Westfal TH Aachen ICE Aachen Germany Rhein Westfal TH Aachen HLTPR Aachen Germany AppTek GmbH Aachen Germany

ISBN: (纸本)9781665494663

As long as a computational precision above 8 bits is preferred, digital design generally outperforms analog one incurring less hardware cost. This motivates our recent studies on digital approximate computing as presented in this paper. Rather than using fixed-point numbers, discrete steps of approximation using floating-point number representations such as BFloat16 and posit formats are explored particularly. time-domain computing is addressed as well which starts in the digital domain with discrete delay values and moves towards the analog domain under increased delay uncertainties when pushed for energy efficiency by voltage scaling. The proposed approximate arithmetic and nonlinear activation functions are further evaluated in various artificial neural networks achieving competitive Quality-of-Service compared to the state-of-the-art with full-precision computing.

关键词： Transcendental functions posits time-domain computing machine learning

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A time-Based Intra-Memory computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2021年第7期56卷 2281-2290页

作者： Everson, Luke R. Sapatnekar, Sachin S. Kim, Chris H. Univ Minnesota Elect & Comp Engn Dept Minneapolis MN 55455 USA

A mixed-signal, time-based 65-nm application-specific integrated circuit is developed for solving shortest-path problems. Digital circuits are collocated with the memory as intra-memory computing. The core follows similar principles from wave routing and, additionally, incorporates a gradient on the periphery of the core to implement the A* algorithm predicted distance heuristic. A leading pulse is propagated from start nodes and is asynchronously latched in neighboring vertex cells and pushed to its four neighbors. Applications include collision avoidance for self-driving cars, shortest path planning, and scientific computing, and are shown to be scalable across many cores. The chip achieves 559 million traversed edges per second at 105 x improved energy efficiency compared with existing platforms such as field-programmable gate array and CPU. The processor operates nominally at 1.79 ns per node with peak power consumption of 26.4 mW.

关键词： Pipelines Routing Random access memory Latches Field programmable gate arrays Partitioning algorithms Art A* algorithm graph computing graphs intra-memory computing single-source shortest path (SSSP) time-domain computing time-to-digital converter

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FlashMAC: A time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2022年第10期57卷 2944-2956页

作者： Gweon, Surin Kang, Sanghoon Kim, Kwantae Yoo, Hoi-Jun Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea Univ Zurich Inst Neuroinformat CH-8057 Zurich Switzerland Swiss Fed Inst Technol CH-8057 Zurich Switzerland

With the widespread of deep neural networks (DNNs) in diverse applications, tiny platforms such as Internet-of-Things devices are starting to adopt DNNs. Due to their extreme energy and form factor constraints, conventional digital-only implementations of multiply-and-accumulate (MAC) acceleration faced fundamental limitations. To that end, the investigation into mixed-signal computing architectures is growing rapidly. Motivated by the flash ADC, this article proposes FlashMAC architecture that can natively support multibit multiplication. In addition, through fusing time- and frequency-domain computing methods without power-hungry oscillators, it enables low latency accumulation with low power consumption. As a result, the proposed time-frequency hybrid architecture achieves high energy efficiency with the support for complex DNN models requiring higher precision. To enhance the robustness of PVT variation of the mixed-signal architecture, a frequency calibration loop is integrated. In addition, motivated by the data-dependent performance of the FlashMAC architecture, variable latency-aware scheduling is proposed. The FlashMAC does not skip MAC operations as zero-skipping architectures do, but the latency of the operation can be lower when operands are smaller in magnitude. Tackling the issue through software and hardware co-optimization, loose synchronization architecture and magnitude-aware weight reordering increase the DNN benchmark performance by achieving higher utilization of the parallel FlashMAC array. The proposed features are integrated into a test chip which is fabricated in 65-nm logic CMOS technology. The silicon chip achieves 56.52 TOPS/W peak energy efficiency and a peak operating frequency of 90 MHz. Tested with the VGG16 benchmark trained on the Imagenet dataset, it achieved 17.04-ms latency while showing 11.15 TOPS/W energy efficiency. As a result, compared to the previous state-of-the-art, the proposed FlashMAC achieved 3.15x higher normalized e

关键词： Analog computing deep learning (DL) frequency-domain computing mixed-signal multiply-and-accumulate (MAC) time-domain computing TinyML

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Scalable time-domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices 23

Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 ...

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Lou, Jie Freye, Florian Lanius, Christian Gemmeke, Tobias Rhein Westfal TH Aachen Integrated Digital Syst & Circuit Design Aachen Germany

ISBN: (纸本)9798400701252

time-domain (TD) computing has attracted attention for its high computing efficiency and suitability for applications on energy-constrained edge devices. In this paper, we present a time-domain compute-in-memory (TDCIM) macro for binary neural networks (BNNs) realized by standard as well as custom delay cells. Multiply- and-accumulate (MAC) operations, batch normalization (BN) and binarization (Bin) are all processed in the time-domain, avoiding costly digital domain post-processing. In addition, it supports flexible mapping for different kernel sizes, achieving 100% utilization. Starting from a standard cell-based implementation, we propose two custom cells that provide interesting trade-offs between energy efficiency, area and accuracy. The two proposed custom designs can achieve 1.5 and 2.06 POPS/W energy efficiencies at 0.5V and 0.6V with less cell area while maintaining model test accuracy.

关键词： time-domain computing compute-in-memory binary neural networks double-edge operation

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A time-domain Parallel Counter for Deep Learning Macro 19

A Time-Domain Parallel Counter for Deep Learning Macro

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19th International SoC Design Conference (ISOCC) - SoC Technology Towards a New Era of Innovation

作者： He, Yixuan Choi, Minsu Kim, Kyung-Ki Kim, Yong-Bin Northeastern Univ Boston MA 02115 USA Missouri Univ Sci Technol Dept ECE Rolla MO USA Daegu Univ Dept Elctron Eng Gyongsan South Korea

ISBN: (纸本)9781665459716

This paper proposes a novel time-domain parallel counter that can handle large number of input bits with good power efficiency and fast speed. This new design turns parallel counting into time-domain accumulation by using two-value delay unit. The circuit is implemented with 63-bit input scheme and simulated using a 65nm CMOS technology with 1V power supply. The results show that the new architecture's speed and power increase linearly with the number of input bits which shows great potential in deep learning implementation where large-number accumulation is needed.

关键词： Parallel counter time-domain computing delay unit

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Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第3期28卷 823-827页

作者： Bavandpour, Mohammad Sahay, Shubham Mahmoodi, Mohammad R. Strukov, Dmitri Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

The widespread and ever-increasing demand for performing in situ inference, signal processing, and other computationally intensive applications in mobile Internet-of-Things (IoT) devices requires fast, compact, and energy-efficient vector-by-matrix multipliers (VMMs). The time-domain VMMs based on emerging nonvolatile memory devices exhibit significantly higher circuit density and energy efficiency than their current-mode counterparts. However, the load capacitors used to accumulate the weighted summation of the inputs in the time-domain-based circuits dominate their energy dissipation and footprint area. The true potential of the time-domain-based VMMs may be realized only when this overhead is minimized. To this end, in this brief, we propose a novel successive integration and rescaling (SIR) approach for implementing a highly efficient mixed-signal time-domain VMM for low-to-medium-precision computing. For a proof of concept, we quantitatively evaluated the performance of the proposed SIR VMM and compared it with the results of the conventional time-domain VMM, using a similar 1T-1R array. Preliminary simulation results for the 4-bit $200\, \times \, 200$ VMM, implemented using a 55-nm technology node, show area and energy efficiencies of 1.33 bits/m(2) and similar to 1.3 POp/J-the numbers, respectively, $\sim 2.5\times $ and $\sim 2.65\times $ higher than those for the prior-work time-domain VMM. Furthermore, we analyze the system-level performance of the proposed SIR VMM engine in the neuromorphic accelerator architectures and provide the preliminary estimates for various deep/recurrent neural network (DNN/RNN) applications.

关键词： 1T-1R memory memristor mixed-signal computing ReRAM successive integration and rescaling (SIR) technique time-domain computing vector-by-matrix multiplier (VMM)

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