A mixed-signal time-based 65-nm application specific integrated circuit is developed for solving shortest-path problems in 3-D. Previous path planning ASICs have been restricted to 2-D maps due to computational comple...
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A mixed-signal time-based 65-nm application specific integrated circuit is developed for solving shortest-path problems in 3-D. Previous path planning ASICs have been restricted to 2-D maps due to computational complexity or physical architecture limitations. Our time-based, asynchronous, one-shot architecture has been coupled with a novel dual axis interleaving strategy to solve the multidimensional shortest path problem in a simple, energy efficient manner. Additional features include circuit-based solutions for obstacle blockage avoidance and gravity. The efficacy of the proposed ASIC is evaluated on a drone navigation application, 3-D Voronoi diagrams, and a physical optics experiment. The chip is twice as energy efficient as prior 2-D work while containing 5x more vertices and 7.5x additional edge connections.
As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requ...
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As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.
We propose an extremely energy-efficient mixed-signal N x N vector-by-matrix multiplication (VMM) in a timedomain. Multi-bit inputs/outputs are represented with time-encoded digital signals, while multi-bit matrix we...
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We propose an extremely energy-efficient mixed-signal N x N vector-by-matrix multiplication (VMM) in a timedomain. Multi-bit inputs/outputs are represented with time-encoded digital signals, while multi-bit matrix weights are realized with adjustable current sources, e.g., transistors biased in subthreshold regime. The major advantage of the proposed approach over other types of mixed-signal implementations is very compact peripheral circuits, which would be essential for achieving high energy efficiency and speed at the system level. As a case study, we have designed a multilayer perceptron, based on two layers of 10 x 10 four-quadrant multipliers, in 55-nm process with embedded NOR flash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that >6 bit operation can be ensured for larger (N > 50) VMMs. Post-layout estimates for 55-nm 6-bit VMM, which take into account the impact of PVT variations, noise, and overhead of I/O circuitry for converting between conventional digital and timedomain representations, show similar to 7 fJ/Op for N > 500. The energy efficiency can be further improved to POp/J regime for more optimal and aggressive designs.
time-domain weighted-sum operation based on a spiking neuron model is discussed and evaluated from a VLSI implementation point of view. This calculation model is useful for extremely low-power operation because transi...
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ISBN:
(数字)9783319466873
ISBN:
(纸本)9783319466873;9783319466866
time-domain weighted-sum operation based on a spiking neuron model is discussed and evaluated from a VLSI implementation point of view. This calculation model is useful for extremely low-power operation because transition states in resistance and capacitance (RC) circuits can be used. Weighted summation is achieved with energy dissipation on the order of 1 fJ using the current CMOS VLSI technology if 1 G Omega order resistance can be used, where the number of inputs can be more than a hundred. This amount of energy is several orders of magnitude lower than that in conventional digital processors. In this paper, we show the software simulation results that verify the proposed calculation method for a 500-input neuron in a three-layer perceptron for digit character recognition.
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