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25th Euromicro Conference on Digital System Design (DSD)

作者： Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9781665474047

Real-time systems need time-predictable computers to guarantee that computation can be performed within a given deadline. For worst-case execution time analysis we need detailed knowledge of the processor and memory architecture. Providing the design of a processor in open source enables the development of worst-case execution time analysis tools without the unsafe reverse engineering of processor architectures. As an example project, we will present T-CREST, an open-source, time-predictable multicore platform for real-time systems. The project started within an EU-funded project. Most artifacts have been put into open-source, greatly simplifying the cooperation and also the further adaption of T-CREST in further research work. Furthermore, open-source enables reproducibility and therefore increases the confidence

关键词： open-source time-predictable computer architecture real-time systems

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Data cache organization for accurate timing analysis

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REAL-time SYSTEMS 2013年第1期49卷 1-28页

作者： Schoeberl, Martin Huber, Benedikt Puffitsch, Wolfgang Tech Univ Denmark Dept Informat & Math Modeling DK-2800 Lyngby Denmark Vienna Univ Technol Inst Comp Engn A-1040 Vienna Austria

Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

关键词： WCET analysis Data caches time-predictable computer architecture

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T-CREST: time-predictable multi-core architecture for embedded systems

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JOURNAL OF SYSTEMS architecture 2015年第9期61卷 449-471页

作者： Schoeberl, Martin Abbaspour, Sahar Akesson, Benny Audsley, Neil Capasso, Raffaele Garside, Jamie Goossens, Kees Goossens, Sven Hansen, Scott Heckmann, Reinhold Hepp, Stefan Huber, Benedikt Jordan, Alexander Kasapaki, Evangelia Knoop, Jens Li, Yonghui Prokesch, Daniel Puffitsch, Wolfgang Puschner, Peter Rocha, Andre Silva, Claudio Sparso, Jens Tocchi, Alessandro Tech Univ Denmark Lyngby Denmark Czech Tech Univ CR-16635 Prague Czech Republic Univ York York YO10 5DD N Yorkshire England Intecs SpA Rome Italy Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Open Grp Brussels Belgium AbsInt Angew Informat GmbH Saarbrucken Germany Vienna Univ Technol Vienna Austria GMV Lisbon Portugal

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding. The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7. The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Real-time systems time-predictable computer architecture

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Worst-case execution time analysis-driven object cache design

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2012年第8期24卷 753-771页

作者： Huber, Benedikt Puffitsch, Wolfgang Schoeberl, Martin Vienna Univ Technol Inst Comp Engn A-1040 Vienna Austria Tech Univ Denmark Dept Informat & Math Modeling Copenhagen Denmark

Hard real-time systems need a time-predictable computing platform to enable static worst-case execution time (WCET) analysis. All performance-enhancing features need to be WCET analyzable. However, standard data caches containing heap-allocated data are very hard to analyze statically. In this paper we explore a new object cache design, which is driven by the capabilities of static WCET analysis. Simulations of standard benchmarks estimating the expected average case performance usually drive computer architecture design. The design decisions derived from this methodology do not necessarily result in a WCET analysis-friendly design. Aiming for a time-predictable design, we therefore propose to employ WCET analysis techniques for the design space exploration of processor architectures. We evaluated different object cache configurations using static analysis techniques. The number of field accesses that can be statically classified as hits is considerable. The analyzed number of cache miss cycles is 346% of the access cycles needed without a cache, which agrees with trends obtained using simulations. Standard data caches perform comparably well in the average case, but accesses to heap data result in overly pessimistic WCET estimations. We therefore believe that an early architecture exploration by means of static timing analysis techniques helps to identify configurations suitable for hard real-time systems. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： real-time systems time-predictable computer architecture worst-case execution time analysis data cache

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Towards Dual-Issue Single-Path Code 23

Towards Dual-Issue Single-Path Code

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IEEE 23rd International Symposium on Real-time Distributed Computing (ISORC)

作者： Maroun, Emad Jacob Schoeberl, Martin Puschner, Peter Vienna Univ Technol Inst Comp Engn Vienna Austria Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9781728169583

The Patmos instruction-set architecture is designed for real-time systems. As such, it has features that increase the predictability of code running on it. One important feature is its dual-issue pipeline: instructions may be organized in bundles of two that are issued and executed in parallel. This increases the throughput of the processor in a predictable manner, but only if the compiler makes use of it. Single-path code is a code-generation technique that produces predictable executions by always following the same trace of instructions. The Patmos compiler can already produce single-path code, but it does not use the second issue slot available in the processor. This is less than ideal because the singlepath transformation results in code that has a high degree of instruction-level parallelism. In this paper, we present a single-path code generator that can produce bundled instructions. It includes generic support for bundling algorithms, such that implementing them is simple and does not require changing other parts of the compiler. We also present one such bundling algorithm plugged into the single-path code generator. With it, we show that we can produce dual-issue instructions to improve performance.

关键词： real-time systems time-predictable computer architecture single-path code generation

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Towards Lingua Franca on the Patmos Processor 27

Towards Lingua Franca on the Patmos Processor

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27th International Symposium on Real-time Distributed Computing (ISORC)

作者： Khodadad, Ehsan Pezzarossa, Luca Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9798350371291;9798350371284

Real-time embedded systems demand higher reliability than any other computer systems. These systems require special modeling paradigms to satisfy time constraints. This paper introduced a design method by combining T-CREST, a time-predictable multi-core hardware, with Lingua Franca, a coordination framework that generates deterministic time-predictable code. We executed a Lingua Franca piece of software on T-CREST platform and performed preliminary experiments demonstrating its correct functionality.

关键词： T-CREST Lingua Franca real-time systems time-predictable computer architecture WCET Analysis

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Two-Step Register Allocation for Implementing Single-Path Code 27

Two-Step Register Allocation for Implementing Single-Path Co...

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27th International Symposium on Real-time Distributed Computing (ISORC)

作者： Maroun, Emad Jacob Schoeberl, Martin Puschner, Peter TU Wien Inst Comp Engn Vienna Austria Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9798350371291;9798350371284

Register allocation is a crucial step in the compilation pipeline that decides what program values occupy which physical registers. Single-path code's use of predicated instructions instead of branching control-flow means register allocation must also allocate predicate registers. In this paper, we improve the original single-path transformation to allow generic register allocators to allocate predicate registers. Our improved transformation splits register allocation into two. First, the general-purpose registers are allocated as usual using a generic register allocator. Then, the main steps of the single-path transformation are performed while still using virtual predicate registers. Lastly, register allocation is rerun using the generic allocator to allocate the predicate registers. Our results show the improved single-path transformation increasing performance by up to 80 % and reducing code size by up to 43 % compared to the original transformation that uses a custom predicate allocator.

关键词： real-time systems time-predictable computer architecture single-path constant execution time

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Exploration of Network Interface architectures for a Real-time Network-on-Chip 27

Exploration of Network Interface Architectures for a Real-Ti...

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27th International Symposium on Real-time Distributed Computing (ISORC)

作者： Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9798350371291;9798350371284

Network interfaces play a central role in multicore architectures that use a network-on-chip for communication. Network interface designs have not received much attention in the research community despite this central role. This paper explores different network interface configurations for a real-time network-on-chip architecture. We evaluate the effects of different FIFO queue organizations on the bandwidth and maximum latency of messages in a time-division multiplexing network-on-chip.

关键词： network-on-chip network interface real-time systems time-predictable computer architecture

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Multicore Models of Communication for Cyber-Physical Systems 9th

Multicore Models of Communication for Cyber-Physical Systems

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9th International Workshop on Model-Based Design of Cyber Physical Systems (CyPhy) / 15th International Workshop on Embedded and Cyber-Physical Systems Education (WESE)

作者： Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9783030411312;9783030411305

Cyber-physical systems are systems where the environment interacts with computers (the cyber part) with real-time constraints. Emerging technologies, such as artificial intelligence and machine learning, call for ever-increasing processing power. However, for real-time systems, we need to prove statically that this processing demand can be performed within strict deadlines. This paper explores a time-predictable multicore architecture for those demanding cyber-physical systems. We explore different models of communication between those multiple cores. We compare the message passing model on top of a network-on-chip with message passing on two forms of shared scratchpad memory.

关键词： Real-time systems Multicore communication time-predictable computer architecture

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Compiler-Directed Constant Execution time on Flat Memory Systems 26

Compiler-Directed Constant Execution Time on Flat Memory Sys...

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26th IEEE International Symposium on Real-time Distributed Computing (ISORC)

作者： Maroun, Emad Jacob Schoeberl, Martin Puschner, Peter TU Wien Inst Comp Engn Vienna Austria Tech Univ Denmark Dept Appl Math & Comp Sci Lyngby Denmark

ISBN: (纸本)9798350339024

time predictability is a central requirement for real-time systems. The correct behavior of such a system can only be achieved if the results of programs are ready in time to affect the environment. Execution times of modern systems can vary for many reasons, meaning complex analyses must be performed to ensure that the execution time is bounded and that a task always finishes before its deadline. Care must also be taken to ensure that nefarious actors do not exploit the varying execution time to compromise the system's integrity. Avoiding variable execution times can greatly simplify systems, is inherently more secure, and eliminates the need for complex analyses. In this paper, we first argue for the value of having programs with constant execution times. We then show how the memory system around a processing core can affect execution times even on systems without intermediate storage like caches or scratch-pads. We present automatic compiler techniques for generating constant execution time programs and evaluate their implementation on the Patmos architecture. We show that combining our two compensation techniques is generally superior to either on their own. We compare the performance of our implementation to the estimates produced by the Platin worst-case execution time analyzer. While our implementation significantly impacts performance, it is generally manageable and has the potential for comparable execution times.

关键词： real-time systems time-predictable computer architecture single-path constant execution time

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