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19th International Conference on Engineering of Complex Computer Systems (ICECCS)

作者： Zeng, Naiju Zhang, Wenhui Chinese Acad Sci Inst Software State Key Lab Comp Sci Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781479954827

transaction level modeling (TLM) is a high-level approach to modeling digital systems where details of communication are separated from the details of computation. In SystemC transaction level models, modules communicate through function calls provided by channels, which include primitive channels and hierarchical channels. This work 1 extends the semantics of simple SystemC models in previous work to support the key concepts of SystemC transaction level models and presents a tool to transform SystemC source codes in TLM-1.0 to transition systems for the purpose of verification on symbolic model checker VERDS. Our approach is demonstrated through a case study of an abstract bus implemented in TLM-1.0 of SystemC.

关键词： formal semantics SystemC transaction level model VERDS

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Interface synthesis for heterogeneous multi-core systems from transaction level models 07

Interface synthesis for heterogeneous multi-core systems fro...

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Conference on Languages, Compilers and Tools for Embedded Systems

作者： Cho, Hansu Abdi, Samar Gajski, Daniel Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

ISBN: (纸本)9781595936325

This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters in the platform and generates interface modules called universal bridges between buses in the design. The design and configuration of the bridges depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the bridge can be automatically derived based on these parameters. We use industrial strength design drivers such as an MP3 decoder to test our automatically generated bridges for a variety of platforms and compare them to manually designed bridges on different quality metrics. Our experimental results show that performance of automatically generated bridges are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 5 orders of improvement in development time.

关键词： HW-SW co-design communication synthesis interface synthesis universal bridge transaction level model channel performance design reliability experimentation verification

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SystemC transaction level models and RTL verification

SystemC transaction level models and RTL verification

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43rd Design Automation Conference

作者： Swan, Stuart Cadence Design Syst Inc San Jose CA 95134 USA

ISBN: (纸本)1595933816

This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models.

关键词： standardization languages verification SystemC transaction level model TLM RTL verification hardware/software co-design hardware/software co-verification

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Interface synthesis for heterogeneous multi-core systems from transaction level models

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ACM SIGPLAN NOTICES 2007年第7期42卷 140-142页

作者： Cho, Hansu Abdi, Samar Gajski, Daniel Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92717 USA

关键词： HW-SW co-design communication synthesis interface synthesis universal bridge transaction level model channel performance design reliability experimentation verification

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Communication architecture design for reconfigurable multimedia SoC platform

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2010年第1期14卷 1-20页

作者： Lee, Ganghee Ahn, Yongjin Lee, Seokhyun Son, Jeongki Yoon, Kiwook Choi, Kiyoung Seoul Natl Univ Seoul South Korea CORELOGIC Ltd Soft Dev Div Seoul South Korea

Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.

关键词： Multiprocessor system-on-chip transaction level model Coarse-grained reconfigurable architecture Schedule Design space exploration

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A mixed-level virtual prototyping environment for SystemC-based design methodology

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MICROELECTRONICS JOURNAL 2009年第7期40卷 1082-1093页

作者： Park, Sanggyu Yoon, Sangyong Chae, Soo-Ik Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea

We propose a flexible mixed-level virtual prototyping environment, where models in different abstraction levels such as transaction level, register-transfer level, and software level can be co-simulated together. In the proposed environment, the designers should capture a transaction level system model before hardware-software partitioning, from which mixed-level virtual prototyping models can be refined with pre-defined and pre-verified communication primitives. We explain several techniques employed in the environment such as ID ports for software template efficiency, abstraction adapters in SystemC for mixed level simulation, and trace-driven simulation for faster performance evaluation. Moreover, transaction level descriptions in SystemC can be compiled and executed as software together with the DEOS, which is an operating system that provides SystemC APIs. We Compared the simulation speed of several mixed-level virtual prototypes of a H.264 decoder to show the effectiveness of the proposed environment. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： SystemC transaction level model Channel Architecture template Virtual prototype

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Development of a Virtual Platform for IP and Firmware Verification 11

Development of a Virtual Platform for IP and Firmware Verifi...

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International SoC Design Conference (ISOCC)]

作者： Shin, Changmin Kim, Yongjoo Elect & Telecommun Res Inst Embedded Software Res Div Daejeon South Korea

ISBN: (纸本)9781479951277

The proposed virtual platform in this paper is composed of the basic IP models and has an integrated simulation functionality. The basic TLM models used to build a virtual platform are ARM9 processor core, memory, AMBA bus, displays, and system peripherals. And these TLM models are connected to each other. The virtual platform is built by porting the IP TLM model for the IP verification on the previous virtual platform. And the firmware for IP operation is developed. The operation and verification of the IP model are performed by simulating the newly formed virtual platform. In this paper, the verification of UART, Camera IP, and face recognition IP was performed by using the integrated simulation of the constructed virtual platform. With the integration simulation of virtual platform developed in this paper, it is possible to develop both the IP and the firmware simultaneously. Therefore, the development period is shortened.

关键词： Intellectual Property transaction level model Register Transfer level Cycle level model

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Design Exploration and Automatic Generation of MPSoC Platform TLMs from Kahn Process Network Applications 10

Design Exploration and Automatic Generation of MPSoC Platfor...

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ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tool for Embedded Systems

作者： Viskic, Ines Yu, Lochi Gajski, Daniel Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA USA

ISBN: (纸本)9781605589534

With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, transaction level modeling and Platform Aware Design are seen as promising approaches to efficient MPSoC design. In this paper, we present an automatized 3-phase process of Platform Aware Design and apply it to Kahn Process Networks (KPN) applications, a widely used model of computation for data-flow applications. We start with the KPN application and an abstract platform template and automatically generate an executable TLM with estimated timing that accurately reflects the system platform. We support homogeneous and heterogeneous multi-master platform models with shared memory or direct communication paradigm. The communication in heterogeneous platform modules is enabled with the transducer unit (TX) for protocol translation. TX units also act as message routers to support Network on Chip (NoC) communication. We evaluate our approach with the case study of the H.264 Encoder design process, in which the specification compliant design was reached from the KPN application in less than 2 hours. The example demonstrates that automatic generation of platform aware TLMs enables a fast, efficient and error resilient design process.

关键词： Kahn process automatic generation process mapping process network transaction level model

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Supporting Linux on Virtual Platform based on Versatile Express Board 11

Supporting Linux on Virtual Platform based on Versatile Expr...

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International SoC Design Conference (ISOCC)]

作者： Shin, Changmin Kim, Yongjoo Elect & Telecommun Res Inst Embedded Software Res Div Daejeon South Korea

ISBN: (纸本)9781479951277

In general, when a embedded system is to be developed, the device drivers, operating system, and the application softwares are developed after the hardware of a embedded system is developed. If the hardware and software are developed at the same time, the development time and cost savings of the embedded system are possible. This paper defines and designs the structure of a SW-SoC Convergence Platform that is a virtual platform for supporting the concurrent development of the hardware and software. The hardware of the SW-SoC Convergence Platform is implemented using virtual prototypes for ARM Versatile Express Board that is widely used as an embedded reference system. The operating systems (i.e., Ubuntu Desktop V12.11, Ubuntu Nano V13.08) were ported to the virtual platform. Accordingly, using the operating system ported to the SW-SoC Convergence Platform, the actual application software 's development is possible before the real hardware is developed.

关键词： Virtual Platform Intellectual Property transaction level model SoC

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Separation of Communication and Computation in SystemC/TLM modeling: a Feature-Oriented Approach

Separation of Communication and Computation in SystemC/TLM m...

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12th International Symposium on Quality Electronic Design (ISQED)

作者： Ye Jun Tan Qingping Li Tun Natl Univ Def Technol Sch Comp Sci Changsha Hunan Peoples R China

ISBN: (纸本)9781612849140

Separation of Concern is a fundamental principle of software engineering. Considering that SystemC/TLM models are in fact software programs that simulating hardware behavior, this principal should also be followed in SystemC/TLM modeling and one of its applications is the Separation of Communication and Computation (CC separation). However, plenty of existing SystemC/TLM models haven't actually separated CC, thus caused much redundant developing effort when changing their computation model or communication protocol. In this paper, we propose to use Feature-Oriented Programming (FOP) methodology to separate CC in SystemC/TLM modeling, and compare it with Object-Oriented approaches. The comparison shows the advantages of our Feature-Oriented approach.

关键词： Separation of Communication and Computation SystemC transaction level model Feature-Oriented Programming

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