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LINEAR QUADTREE ALGORITHMS FOR transputer array

IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1990年第1期137卷 114-128页

作者： MASON, DC Department of Geography NERC Unit for Thematic Information Systems University of Reading Reading UK

The quadtree is a hierarchical data model based upon a regular recursive decomposition of space, which has been found useful in such areas as image processing, computer graphics, cartography and spatial information systems. The linear quadtree is a pointerless representation of the quadtree. In the paper, a number of linear quadtree algorithms are presented for a transputer array. These form a largely complementary set to those developed by Bhaskaret al.[1] for a similar multiprocessor architecture. Emphasis is placed on algorithms which require the neighbours of quadtree leaves to be accessed. These include perimeter computation, connected component labelling and image dilation. A quadtree generation algorithm is also described. Timing estimates have been carried out using a transputer development system. A price to be paid for the speed increases achieved is an increase in the complexity of the multiprocessor algorithms.

关键词： multiprocessing systems perimeter computation regular recursive decomposition trees (mathematics) cartography image processing Computer architecture connected component labelling hierarchical data model parallel algorithms cellular arrays computer graphics transputer array complexity Programming and algorithm theory spatial information systems linear quadtree algorithms multiprocessor architecture

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A PARALLEL ALGORITHM FOR THE DENSE SYMMETRICAL EIGENVALUE PROBLEM ON A transputer array

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PARALLEL COMPUTING 1992年第2期18卷 207-212页

作者： KALAMBOUKIS, TZ Athens University of Economics Department of Informatics 76 Patission Street Athens 104 34 Greece

In this paper we present an efficient implementation of a parallel algorithm for the determination of the eigenvalues of dense real symmetric matrices. Our approach relies on the reduction of a real symmetric full matrix to tridiagonal form applying Householder's transformations. Performance results of the algorithm on a transputer array are presented with particular emphasis given to speed-ups over classical EISPACK algorithms.

关键词： EIGENVALUES EIGENVECTORS transputer array PERFORMANCE RESULTS

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MONTE-CARLO SIMULATION ON transputer arrayS

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PARALLEL COMPUTING 1988年第2期6卷 247-258页

作者： ASKEW, CR CARPENTER, DB CHALKER, JT HEY, AJG MOORE, M NICOLE, DA PRITCHARD, DJ Department of Physics University of Southampton Southampton SO9 5NH United Kingdom

A Monte Carlo simulation of a simple statistical physics model is decomposed onto a multi-processor (transputer) array in two essentially different ways: using ‘geometric’ and ‘algorithmic’ concurrency. The geometric decomposition (in which each processor handles a small sector of the physical system) is characterized by high efficiency in utilization of processors, and relative simplicity in programming. The algorithmic decomposition (in which each processor handles a small sub-task of the full algorithm, typically in a pipelined mode) is characterized by greater flexibility in the data-size (size of the physical system) and minimal memory requirements for a majority of the processors in the array. These assertions are made concrete in relation to our specific problem (a two-dimensional spin system simulation) which is, in many respects representative of a wide class of problems of interest to theoretical physicists.

关键词： Monte Carlo simulation Multiprocessors parallelism parallelization transputer array two-dimensional spin system simulation

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A MULTIPROCESSOR SYSTEM FOR VISUAL COMMUNICATIONS USING DISTRIBUTED transputer arrayS

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MICROPROCESSORS AND MICROSYSTEMS 1994年第2期18卷 79-87页

作者： DUH, WJ WU, JL HUANG, JH Communication and Multimedia Research Laboratory Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan R.O.C.

A-transputer-based multiprocessor system for visual communication applications is presented. H.261, the encoding/decoding standard for video telephones recommended by CCITT, is implemented in this system for demonstration. Fundamental video processing operators, such as 3 x 3 discrete Laplacian, are also implemented. Up to 20.4 frames per second (fps) video replaying rate and about 7.2 fps processing rate for executing 3 x 3 linear filtering are obtained. Analyses and guidelines for designers wishing to build multiprocessor systems for visual communications are also given. Such a system is fast and flexible for experimenting with new algorithms and is an excellent CAI (computer aided instruction) tool in teaching video processing.

关键词： VIDEO TELEPHONE transputer array

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EVALUATION OF A SPECTRAL ELEMENT CFD CODE ON PARALLEL ARCHITECTURES

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PARALLEL COMPUTING 1995年第7期21卷 1137-1150页

作者： FLOROS, N REEVE, JS UNIV SOUTHAMPTON DEPT ELECTR & COMP SCISOUTHAMPTON SO17 1BJHANTSENGLAND

We present an evaluation of a Spectral Element Navier-Stokes solver on three generations of parallel architecture. The parallel platforms used are a network of transputers, an Intel iPSC/860 and a Meiko CS2. While performance on the older transputer and iPSC/860 machines is fairly predictable, the behaviour of the code on the SPARC-10 based Meiko CS2 demonstrated the influence of the internal memory hierachy on performance. These effects give the code problem dependent performance parameters that makes scaling properties difficult to quantify. Our code however, seems future proof, provided sufficiently large problems can be found to overcome the relatively large communications costs with respect to the processor speed.

关键词： INCOMPRESSIBLE NAVIER-STOKES COMPUTATIONAL FLUID DYNAMICS transputer array HYPERCUBE DISTRIBUTED MEMORY MULTIPROCESSOR

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A TRIDIAGONAL SOLVER FOR MASSIVELY PARALLEL COMPUTER-SYSTEMS

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PARALLEL COMPUTING 1990年第2-3期16卷 361-368页

作者： REALE, F Osservatorio Astronomico di Palermo Palermo Italy

This paper describes a parallel solver of tridiagonal systems appropriate for distributed memory computers and implemented on an array of chain-connected T800 transputers. Each processor in the chain uses the same program to solve its own subset of equations. This implementation is suited, for instance, for solving the heat conduction equation in one-dimensional hydrodynamic codes. The procedure performs a parallel cyclic reduction, a recursive Gaussian elimination on a reduced number of equations and a parallel backward unfolding scheme, with a direct substitution in the reduced equations. The code has been written in Occam2 language. A one-way communication of values between adjacent processors is required at each cycle of both the reduction and the unfolding steps. Due to the number of floating point operations and the amount of communications the implementation described here works efficiently on arrays with more than 4 processors and for more than approximately 15 equations per processor.

关键词： TRIDIAGONAL LINEAR SYSTEMS PARALLEL CYCLIC REDUCTION IMPLEMENTATION FEATURES DISTRIBUTED-MEMORY MULTIPROCESSOR transputer array

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SIMULATING MODULAR NEURAL NETWORKS ON MESSAGE-PASSING MULTIPROCESSORS

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PARALLEL COMPUTING 1991年第4-5期17卷 361-379页

作者： TOLLENAERE, T ORBAN, GA Katholieke Universiteit Leuven Laboratory for Neuro- and Psychophysiology Campus Gasthuisberg Herestraat B-3000 Leuven Belgium

While simulation programs for single neural networks, running on parallel machines, always use a fixed problem decomposition and mapping strategy, we show that this is not possible for modular neural networks. We demonstrate this by analysing decomposition and mapping issues for a particular modular neural network model: the entropy-driven artificial neural network. The classic approach to simulations consists of two steps: first a data structure is built, describing the problem to be simulated. For a neural network this data structure contains the network topology, the interconnection strengths, etc. In a second step, this data structure is read into the simulation program, which performs a fixed decomposition and mapping before simulation can take place. Since this approach cannot be used any more for simulations of modular networks, we propose a new, three-step approach, in which decomposition and mapping are taken out of the simulation program. A compiler is used to prepare the problem data structure, a splitter program takes care of problem decomposition, and the simulator program takes the decomposed problem as its input. Since all decisions with respect to decomposition and mapping are taken by the splitter, the simulator program is independent of decomposition and mapping, and hence it can handle any decomposition and mapping. Following this approach, a machine-independent simulation environment was designed, and this design was implemented on a transputer system. To show that our approach is generic (i.e. not limited to simulations of modular networks) an implementation of a Hopefield network for image restoration is described. In spite of the classic preconceptions about generic software, performance analysis and benchmark results show that our novel, generic approach can be implemented efficiently on transputer arrays.

关键词： MODULAR NEURAL NETWORKS PROBLEM DECOMPOSITION MAPPING PROBLEM transputer array PARALLEL PROCESSING

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THE PARALLEL QR FACTORIZATION ALGORITHM FOR TRIDIAGONAL LINEAR-SYSTEMS

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PARALLEL COMPUTING 1995年第7期21卷 1097-1110页

作者： AMODIO, P BRUGNANO, L UNIV FLORENCE DIPARTIMENTO ENERGETI-50134 FLORENCEITALY

We describe a new parallel solver in the class of partition methods for general, nonsingular tridiagonal linear systems. Starting from an already known partitioning of the coefficient matrix among the parallel processors, we define a factorization, based on the QR factorization, which depends on the conditioning of the sub-blocks in each processor. Moreover, also the reduced system, whose solution is the only scalar section of the algorithm, has a dimension which depends both on the conditioning of these sub-blocks, and on the number of processors. We analyze the stability properties of the obtained parallel factorization, and report some numerical tests carried out on a net of transputers.

关键词： TRIDIAGONAL LINEAR SYSTEMS PARALLEL SOLVERS QR FACTORIZATION transputer array

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transputer CONTROL OF A PUMA-560 ROBOT VIA THE VIRTUAL BUS

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IEE PROCEEDINGS-D CONTROL THEORY AND APPLICATIONS 1990年第4期137卷 245-252页

作者： DANIEL, RW SHARKEY, PM Robotics Research Group Department of Engineering Science Oxford University Oxford UK

The robot control problem is discussed with regard to controller implementation on a multitransputer array. Some high-performance aspects required of such controllers are described, with particular reference to robot force control. The implications for the architecture required for controllers based on computed torque are discussed and an example is described. The idea of treating a transputer array as a virtual bus is put forward for the implementation of fast real-time controllers. An example is given of controlling a Puma 560 industrial robot. Some of the practical considerations for using transputers for such control are described.

关键词： Computer architecture industrial robots Control engineering computing Control technology and theory Manufacturing processes Robotics computerised control parallel architectures industrial robot transputer array Mechanical variables control Puma 560 Control applications in manufacturing processes Industrial applications of IT force control real-time virtual bus multitransputer

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A parallel algorithm for fixed-dimensional linear programming

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Parallel Algorithms and Applications 1995年第1期6卷 17-24页

作者： Kuzyurin, Nikolai N. Shabanov, Leonid V. Institute of System Programming Russian Academy of Science Moscow 109004 B. Communisticheskaja 25 Russian Federation

Simple parallel algorithm for fixed-dimensional Linear Programming is developed. It provides a straight-forward implementation on MIMD architectures with high efficiency. The implementation on transputer arrays is described and numerical results of performance are presented. © 1995, Taylor & Francis Group, LLC. All rights reserved.

关键词： Linear programming MIMD architecture transputer array

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