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An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata

MICROPROCESSORS AND MICROSYSTEMS 2017年 53卷 157-167页

作者： Deb, Arighna Das, Debesh K. Jadavpur Univ Dept Comp Sci & Engn Kolkata India

In recent years, majority-logic received significant attention as a synthesis approach for large Boolean functions. This logic is easily implemented in Quantum-dot cellular automata (QCA) technology which is emerging as an alternative to CMOS technology. In fact, majority logic gate serves as the basic logic unit in the digital design of QCA circuits. This paper introduces a synthesis technique for implementing totally symmetric Boolean functions using majority logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3-input majority gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. Comparison with existing synthesis approaches confirms the efficacy of our method. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Quantum-dot cellular automata Majority gate Symmetric functions unate functions

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Transistor Stuck-on Fault Detection Tests for Digital CMOS Circuits 21

Transistor Stuck-on Fault Detection Tests for Digital CMOS C...

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21st IEEE European Test Symposium (ETS)

作者： Lin, Xijiang Reddy, Sudhakar M. Rajski, Janusz Mentor Graph Corp Wilsonville OR 97070 USA Univ Iowa ECE Dept Iowa City IA USA

ISBN: (纸本)9781467396592

Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

关键词： Transistor Stuck-on Faults Test Generation Fault Detection Maximal False and Minimal True Vertices unate functions

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Transistor Stuck-on Fault Detection Tests for Digital CMOS Circuits

Transistor Stuck-on Fault Detection Tests for Digital CMOS C...

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European Test Symposium

作者： Xijiang Lin Sudhakar M. Reddy Janusz Rajski Mentor Graphics Corporation Wilsonville OR USA ECE Department University of Iowa Iowa City IA USA

ISBN: (纸本)9781467396608

Typically I_(DDQ) measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using I_(DDQ) measuremen ts is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed I_(DDQ) based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

关键词： Transistor Stuck-on Faults Test Generation Fault Detection Maximal False and Minimal True Vertices unate functions

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A Regular Network of Symmetric functions in Quantum-Dot Cellular Automata

A Regular Network of Symmetric Functions in Quantum-Dot Cell...

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18th International Symposium on VLSI Design and Test

作者： Deb, Arighna Das, Debesh K. Jadavpur Univ Kolkata India

ISBN: (纸本)9781479940066

Quantum-dot cellular automata (QCA) is a technology which has the potential of faster speed, smaller size and minimum power consumption compared to transistor based technology. In quantum-dot cellular automata, the basic elements are simple cells. The cells are used to construct majority voter gate, inverter and wire. This paper utilizes the unique characteristics of QCA majority voter gate to realize symmetric functions. In this paper, we introduce a synthesis technique for implementing totally symmetric Boolean functions using Quantum-dot Cellular Automata (QCA) logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3 input majority voter gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. The designs are simulated and the simulation result indicates the complexity, area and delay of the proposed designs.

关键词： Majority Voter Gate Quantum-dot cellular automata Symmetric functions unate functions

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Properties of Boolean networks and methods for their tests

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EURASIP JOURNAL ON BIOINFORMATICS AND SYSTEMS BIOLOGY 2013年第1期2013卷 1-1页

作者： Klotz, Johannes Georg Feuer, Ronny Sawodny, Oliver Bossert, Martin Ederer, Michael Schober, Steffen Univ Ulm Inst Commun Engn Albert Einstein Allee 43 D-89081 Ulm Germany Univ Stuttgart Inst Syst Dynam D-70569 Stuttgart Germany

Transcriptional regulation networks are often modeled as Boolean networks. We discuss certain properties of Boolean functions (BFs), which are considered as important in such networks, namely, membership to the classes of unate or canalizing functions. Of further interest is the average sensitivity (AS) of functions. In this article, we discuss several algorithms to test the properties of interest. To test canalizing properties of functions, we apply spectral techniques, which can also be used to characterize the AS of functions as well as the influences of variables in unate BFs. Further, we provide and review upper and lower bounds on the AS of unate BFs based on the spectral representation. Finally, we apply these methods to a transcriptional regulation network of Escherichia coli, which controls central parts of the E. coli metabolism. We find that all functions are unate. Also the analysis of the AS of the network reveals an exceptional robustness against transient fluctuations of the binary variables.(a)

关键词： Regulatory Boolean networks Boolean networks Linear threshold functions unate functions Canalizing function Sensitivity Average sensitivity Restricted functions Escherichia coli

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Invalidation of the structure of genetic network dynamics: a geometric approach

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INTERNATIONAL JOURNAL OF ROBUST AND NONLINEAR CONTROL 2012年第10期22卷 1140-1156页

作者： Porreca, Riccardo Cinquemani, Eugenio Lygeros, John Ferrari-Trecate, Giancarlo ETH Inst Automat CH-8092 Zurich Switzerland INRIA Grenoble Rhone Alpes F-38334 Montbonnot St Martin St Ismier France Univ Pavia Dipartimento Informat & Sistemist I-27100 Pavia Italy

This work concerns the identification of the structure of a genetic network model from measurements of gene product concentrations and synthesis rates. In earlier work, we developed a data preprocessing algorithm that is able to reject many hypotheses on the network structure by testing certain monotonicity properties for a wide family of network models. Here, we develop a geometric interpretation of the method. Then, for a relevant subclass of genetic network models, we extend our approach to the combined testing of monotonicity and convexity-like properties associated with the network structures. The theoretical aspects and practical performance of the enhanced methods are illustrated by way of numerical results. Copyright (c) 2012 John Wiley & Sons, Ltd.

关键词： systems biology identification quasi-convexity unate functions sigmoidal activation functions

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Learning the structure of genetic network dynamics: A geometric approach

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IFAC Proceedings Volumes 2011年第1期44卷 11654-11659页

作者： Riccardo Porreca Eugenio Cinquemani John Lygeros Giancarlo Ferrari-Trecate Institut für Automatik ETH Zürich Switzerland INRIA Grenoble-Rhône-Alpes Montbonnot France Dipartimento di Informatica e Sistemistica Università di Pavia Italy

Abstract This work concerns the identification of the structure of a genetic network model from measurements of gene product concentrations and synthesis rates. In earlier work, for a wide family of network models, we developed a data preprocessing algorithm that is able to reject many hypotheses on the network structure by testing certain monotonicity properties of the models. Here we develop a geometric analysis of the method. Then, for a relevant subclass of genetic network models, we extend our approach to the combined testing of monotonicity and convexity-like properties associated with the network structures. Theoretical achievements as well as performance of the enhanced methods are illustrated by way of numerical results.

关键词： Systems Biology Identification Quasiconvexity unate functions Sigmoidal activation functions

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Um algoritmo formal para remoção de redundâncias

Um algoritmo formal para remoção de redundâncias

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作者： Marques, Felipe de Souza

Algorithms for digital circuit design aim the reduction of a cost function composed of four criteria: area, delay, power and testability. Usually these algorithms are able to obtain a trade-off for the optimization of two of these criteria. Undesired effects may occur due to the optimization of one of the criteria. For instance, delay optimizations may introduce non testable stuck-at faults (redundancies) in a circuit, this way reducing its testability. Several logic synthesis algorithms exploit specific properties of the logic functions to be synthesized. One example of function with specific properties are the socalled unate functions. An example of this kind of function is the carry-out sign in a full adder circuit. This kind of function require special care in order to avoid redundancy introduction. Shannon decomposition [SHA 38] is used in many logic synthesis algorithms for improving circuit performance. The general case of the Shannon decomposition is represented by a binate (not unate) equation. Redundancies are introduced in a circuit when a binate equation is used to express a unate function. Binary Decision Diagrams (BDDs) are a kind of data structures widely used in the field of logic synthesis. Shannon decomposition is also used to derive circuits from BDDs. This data structure is used to represent logic functions, but it is not able to maintain an irredundant representation of any logic function. Unfortunately, circuits derived from BDDs will possibly have redundancies, specially when Shannon decomposition is used. Some data structures are able to represent any logic function in a irredundant form. This is the case of the VPBDDs [REI 95a] [REI 2000], which have special properties that preserve the testability properties of the functions being represented. Based on VPBDD properties, a novel algorithm for redundancy removal was proposed [MAR 2002]. This algorithm is able to generate irredundant circuits even when the function represented by the VPBDD i

关键词： Microeletrônica Redundancy removal BBDs False paths Stuck-at faults Remocao : Redundancias Path delay faults BDD VPBDD unate functions Dissertação

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Ordered binary decision diagrams as knowledge-bases

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ARTIFICIAL INTELLIGENCE 2002年第2期136卷 189-213页

作者： Horiyama, T Ibaraki, T Nara Inst Sci & Technol Grad Sch Informat Sci Nara 6300101 Japan Kyoto Univ Grad Sch Informat Dept Appl Math & Phys Kyoto 6068501 Japan

We consider the use of ordered binary decision diagrams (OBDDs) as a means of realizing knowledge-bases, and show that, from the view point of space requirement, the OBDD-based representation is more efficient and suitable in some cases, compared with the traditional CNF-based and/or model-based representations. We then present polynomial time algorithms for the two problems of testing whether a given OBDD represents a unate Boolean function, and of testing whether it represents a Horn function. (C) 2002 Published by Elsevier Science B.V.

关键词： knowledge representation automated reasoning ordered binary decision diagrams (OBDDs) recognition problems unate functions Horn functions

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Negation trees: A unified approach to Boolean function complementation

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IEEE TRANSACTIONS ON COMPUTERS 1996年第5期45卷 626-630页

作者： Wang, Y McCrosky, C Dept. of Comput. Sci. Saskatchewan Univ. Saskatoon Sask. Canada

Boolean function complementation is a basic operation of Boolean algebra. For functions given in SOP form, the complementation methods include the DeMorgan's Law, sharp [3], disjoint sharp [2], unate complementation [4], recursive [4], and Sasao's method [5]. This paper accomplishes three purposes: 1) it exposes an underlying unification of the existing complementation algorithms. it is proven that a) unate-complementation and sharp are the same as the DeMorgan Law algorithm;b) Sasao's algorithm is the same as disjoint sharp;c) disjoint sharp is a special case of the recursive method. 2) it proposes negation trees for the representation of functions and their complements, and 3) it gives faster algorithms for finding complements of functions in SOP form based on negation trees.

关键词： Boolean functions unate functions complementation algorithms negation trees

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