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45th International Conference on Telecommunications and Signal Processing (TSP)

作者： Chiper, Doru Florin Tech Univ Gh Asachi Iasi Dept Dept Appl Elect Iasi Romania Tech Sci Acad Romania ASTR Bucharest Romania Acad Romanian Scientists AOSR Bucharest Romania

ISBN: (数字)9781665469487

ISBN: (纸本)9781665469487

This paper proposes a new vlsi algorithm for a prime length type II generalized discrete Hartley transform (DHT) that allows a high speed vlsi implementation and an efficient incorporation of the obfuscation technique with low overheads. The proposed algorithm is highly regular and modular, presents a low computational complexity, a high throughput and it can be efficiently mapped on linear systolic arrays. Using the obfuscation method, it presents the additional advantage of the hardware security. The proposed vlsi algorithm uses some regular and modular computational structures called quasi-band correlations and can be efficiently implemented on a vlsi chip using the systolic arrays architectural paradigm.

关键词： vlsi algorithms obfuscation hardware security type II generalized DHT transform discrete transforms systolic arrays

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A New vlsi Algorithm for an Efficient vlsi Implementation of Type IV DST based on Short Band-Correlation Structures 13

A New VLSI Algorithm for an Efficient VLSI Implementation of...

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13th International Conference on Communications (COMM)

作者： Chiper, Doru Florin Cotorobai, Laura Teodora Tech Univ Gh Asachi Dept Appl Elect B Dul Carol I 11 Iasi Romania

ISBN: (纸本)9781728156118

A new vlsi algorithm for a prime length DST IV transform that can be efficiently implemented in parallel using linear systolic arrays is presented. The proposed algorithm represent the key for an efficient vlsi implementation with a high throughput and can be efficiently mapped on linear systolic arrays with a small number of I/O channels and a low I/O bandwidth. The proposed algorithm uses an efficient computational structure called pseudo-band correlation structure. It can be implemented as efficient as other similar computation structures as cycle convolution and circular correlation. This leads to an efficient vlsi chip with appealing features from a vlsi implementation point of view as regularity, modularity and short interconnections. We can obtain similar performances as high processing speed, low hardware cost and low I/O costs similar with that obtained using cycle convolution and circular correlation.

关键词： vlsi algorithms discrete transform DST-IV systolic arrays

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A Novel vlsi Algorithm for a Low Complexity vlsi Implementation of DCT Based on Pseudo Circular Correlation Structures 14

A Novel VLSI Algorithm for a Low Complexity VLSI Implementat...

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14th International Symposium on Electronics and Telecommunications (ISETC)

作者： Chiper, Doru Florin Cotorobai, Laura Teodora Tech Univ Gh Asachi Dept Appl Elect Iasi Romania

This paper introduces a novel vlsi algorithm for a low complexity vlsi implementation of DCT based on pseudo circular correlation structures. The proposed method introduces an algorithm which has a computational struc... 详细信息

ISBN: (纸本)9781728189215

关键词： vlsi algorithms DCT systolic arrays

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A Unified vlsi architecture for 1D IDCT and IDST based on pseudo-band correlations 10

A Unified VLSI architecture for 1D IDCT and IDST based on ps...

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10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)

作者： Chiper, Doru Florin Cotorobai, Laura Teodora Tech Univ Gheorghe Asachi Iasi 700050 Romania

ISBN: (纸本)9781538649015

In this paper an efficient unified vlsi architecture for the computation of 1-D IDCT and IDST that have been reformulated to be implemented on the same hardware structure with a minimum modification is presented. The proposed design is based on a new unified vlsi algorithm that can be used to compute both transforms. Using the proposed algorithm an efficient vlsi architecture has been obtained based on the systolic array architectural paradigm with a low hardware complexity and a low number of I/O channels placed at the two ends of the linear array and having a low I/O bandwidth. Moreover the proposed architecture is modular, regular and with local connection favoring a good vlsi implementation.

关键词： vlsi algorithms vlsi architectures Systolic arrays discrete sine transform discrete cosine transform

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A Novel Algorithm and Architecture for a High-Throughput vlsi Implementation of DST using Short Pseudo-cycle Convolutions

A Novel Algorithm and Architecture for a High-Throughput VLS...

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International Symposium on Signals, Circuits and Systems (ISSCS)

作者： Chiper, Doru Florin Cracan, Arcadie Tech Univ Gh Asachi Fac Elect Telecommun & Informat Technol Iasi Romania

ISBN: (纸本)9781538606742

Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new vlsi algorithm that uses short length pseudo-cycle convolution structures for the vlsi implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput vlsi implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays that have a modular and regular structure with a a low I/O cost and local and regular interconnections. Thus, an efficient vlsi implementation with high performances can be obtained.

关键词： vlsi algorithms discrete transforms DST systolic arrays

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A New vlsi Algorithm for a High-Throughput Implementation of Type IV DCT 11

A New VLSI Algorithm for a High-Throughput Implementation of...

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IEEE 11th International Conference on Communications (COMM)

作者： Chiper, Doru Florin Tech Univ Gh Asachi Dept Appl Elect & Inteligent Syst Iasi Romania

ISBN: (纸本)9781467381970

A new design approach based on a new vlsi algorithm for high speed applications of a prime length type IV discrete cosine transform that uses short length cycle convolution structures is presented. It uses a new parallel decomposition method of type IV discrete cosine transform (DCT) that leads to a high throughput vlsi implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays. A vlsi implementation with good performances can be obtained that has a modular and regular structure with a a low I/O cost and local and regular interconnections.

关键词： vlsi algorithms discrete transforms DCT-IV systolic arrays

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An efficient unified framework for implementation of a prime-length DCT/IDCT with high throughput

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2007年第6期55卷 2925-2936页

作者： Chiper, Doru-Morin Swamy, M. N. S. Ahmad, M. Omair Concordia Univ Dept Elect & Comp Engn Ctr Commun & Signal Proc Montreal PQ H3G 1M8 Canada

In this paper, a unified design framework for primelength forward and inverse discrete cosine transforms with a high, throughput is presented. The proposed design facilitates trade-off between the throughput and hardware cost or power consumption, and is well suited for low-power applications. The vlsi structure is highly regular and modular with a topology well suited for the vlsi implementation. The proposed approach is based on the derivation of new efficient systolic algorithms. The algorithms have the same core structure for both the transforms, and the core structure consists of two circular correlations, which unlike other similar computational structures, have the same length and form. Thus, they can be computed in parallel and mapped, on the same linear systolic array with channels having a low I/O bandwidth requirement and their number being independent of the transform length N. Further, it is shown that the two transforms, can be efficiently implemented on the same vlsi chip, where only the pre- and post-processing stages are different. The proposed systolic algorithms retain the benefits provided by vlsi implementations based on circular or cyclic convolution structures, and at the same time has a simpler control structure, high speed and low complexity.

关键词： discrete cosine transform (DCT) high throughput implementation systolic arrays unified DCT/IDCT structure vlsi algorithms

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A systolic array architecture for the discrete sine transform

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2002年第9期50卷 2347-2354页

作者： Chiper, DF Swamy, MNS Ahmad, MO Stouraitis, T Tech Univ Gh Asachi Dept Appl Elect Iasi Romania Concordia Univ Ctr Commun & Signal Proc Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada Univ Patras Dept Elect & Comp Engn Patras Greece

An efficient approach to design very large scale integration (vlsi) architectures and a scheme for the implementation of the discrete sine transform. (DST), based on an appropriate decomposition method that uses circular correlations, is presented. The proposed design uses an efficient restructuring of the computation of the DST into two circular correlations, having similar structures and only one half of the length of the original transform;these can be concurrently computed and mapped onto the same systolic array. Significant improvement in the computational speed can be obtained at a reduced input-output (I/O) cost and low hardware complexity, retaining all the other benefits of the vlsi implementations of the discrete transforms, which use circular correlation or cyclic convolution structures. These features are demonstrated by comparing the proposed design with some of the recently reported schemes.

关键词： discrete sine transform systolic arrays vlsi algorithms

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A novel sorting algorithm and its application to a gamma-ray telescope asynchronous data acquisition system

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NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT 1997年第3期394卷 374-380页

作者： Colavita, A Mumolo, E Capello, G UNIV TRIESTE DEEII-34127 TRIESTEITALY IST NAZL FIS NUCL ICTPMICROPROC LABI-34100 TRIESTEITALY

In this paper we present a novel parallel sorting algorithm, which works through a cascade of elementary sorting units and leads to a scalable architecture. The algorithm's complexity is analyzed and compared with a classical parallel algorithm. It comes out that, although it may be less efficient than classical approaches, the proposed algorithm is highly suited for vlsi implementation for its simplicity and scalability. The paper describes the applications of such device to the asynchronous data acquisition for a gamma-ray telescope.

关键词： gamma-ray telescope sorting algorithms asynchronous data acquisition vlsi algorithms

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Mapping nested loop algorithms into fault-tolerant systolic array architectures

Mapping nested loop algorithms into fault-tolerant systolic ...

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IEEE 1st International Conference on algorithms and Architectures for Parallel Processing (ICA3PP 95)

作者： Esonu, MO AlKhalili, AJ Hariri, S BELL NO RES LTD OTTAWAON K1Y 4H7CANADA

ISBN: (纸本)0780320182

Progress in vlsi and WSI technologies has resulted in the manufacture of special purpose vlsi chips with multiple copies of low-cost processors. These processors can be used to design high performance systems such as systolic arrays. This paper proposes a new systematic approach which can be used to detect and correct errors in systolic array architectures. The approach relies on Space-Time mapping of algorithms into systolic arrays. Fault-tolerant algorithms are designed by introducing redundant computations at the algorithmic level. This is done by deriving several versions of a given algorithm, each of which can be mapped into respective systolic architecture. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of several versions of the algorithm.

关键词： fault-tolerance concurrent error correction redundancy data flow computations vlsi algorithms space-time mapping vlsi architectures systolic arrays systolic architectures parallel processing

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