This paper investigates the dimension reduction and feedback stabilization of max-plus linear systems and applies them to control and optimize the very large scale integration (vlsi) arrayprocessors. We introduce the...
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This paper investigates the dimension reduction and feedback stabilization of max-plus linear systems and applies them to control and optimize the very large scale integration (vlsi) arrayprocessors. We introduce the weakly similar relation between max-plus matrices and the pseudoequivalent relation between autonomous max-plus linear systems, and point out that two systems are pseudoequivalent if and only if their state matrices are weakly similar. The reduced system is defined by using the pseudoequivalence, whose dimension is determined by the row rank of the original state matrix. We focus on obtaining a reduced system which maintains the stability and retains the steady-state period. An algorithm of polynomial complexity is developed to find such a reduced system. The reduced system is then used to design a state feedback controller to stabilize a max-plus linear system. Finally, we use the vlsi array processors as an example to demonstrate how the presented methods work in practical applications.
A systematic procedure to configure fault-tolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed ...
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A systematic procedure to configure fault-tolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed From a target regular algorithm and the transformation onto physical time-processor domain. The resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While it needs sophisticated connection scheme between processing elements to guarantee the fault-tolerance an communication links, the Link complexity is possibly reduced by optimizing redundant operation scheme. Unconstrained and constrained link minimization problems are introduced, and the possibility and the constraints required for link complexity reduction are investigated.
This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessorarray. Based on the notion of computational wavefront, the hardware of the processo...
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This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessorarray. Based on the notion of computational wavefront, the hardware of the processorarray is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduces the complexity of the description of parallel algorithms and simulates the wavefront propagation across the computing network. Together, the hardware and the language lead to a programmable wavefront arrayprocessor (WAP). The WAP blends the advantages of the dedicated systolic array and the general-purpose data-flow machine, and provides a powerful tool for the high-speed execution of a large class of matrix operations and related algorithms which have widespread applications.
In this paper, two fixed size processorarray architectures, which are destined for realization of several linear algebra algorithms, are proposed. In order to implementation of these architecture in modern FPGA devic...
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ISBN:
(纸本)9789665335870
In this paper, two fixed size processorarray architectures, which are destined for realization of several linear algebra algorithms, are proposed. In order to implementation of these architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed, which is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families. It allows to reduce the hardware complexity of the new AU up to 4,5 times in comparison with similar AUs operating with float-point numbers, without decreasing of AU performance and increasing round off errors.
In this paper, the fixed size processorarray architecture, which is destined for realization of LLT-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to impl...
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ISBN:
(纸本)9788392263241
In this paper, the fixed size processorarray architecture, which is destined for realization of LLT-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to implementation of this architecture in modem FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. This AU is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families and its hardware complexity is up to 4,5 times less in comparison with similar AUs operating with float-point numbers.
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