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检索条件"主题词=VLSI Array Processor"
5 条 记 录,以下是1-10 订阅
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Dimension Reduction and Feedback Stabilization for Max-Plus Linear Systems and Applications in vlsi array processors
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IEEE TRANSACTIONS ON AUTOMATIC CONTROL 2017年 第12期62卷 6353-6368页
作者: Wang, Cailu Tao, Yuegang Yang, Peng Liu, Zuojun Hebei Univ Technol Sch Control Sci & Engn Tianjin 300130 Peoples R China
This paper investigates the dimension reduction and feedback stabilization of max-plus linear systems and applies them to control and optimize the very large scale integration (vlsi) array processors. We introduce the... 详细信息
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A systematic design of fault tolerant systolic arrays based on triple modular redundancy in time-processor space
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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1996年 第12期E79D卷 1676-1689页
作者: Kaneko, M Miyauchi, H School of Information Science Japan Advanced Institute of Science and Technology Ishikawa-ken 923-12 Japan Department of Physical Electronics Tokyo Institute of Technology Tokyo 152 Japan Toshiba Co.
A systematic procedure to configure fault-tolerant systolic arrays based on Triplicated Triple Modular Redundancy is proposed. The design procedure consists of the triplication of the dependence graph which is formed ... 详细信息
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WAVEFRONT array processor - LANGUAGE, ARCHITECTURE, AND APPLICATIONS
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IEEE TRANSACTIONS ON COMPUTERS 1982年 第11期31卷 1054-1066页
作者: KUNG, SY ARUN, KS GALEZER, RJ RAO, DVB Department of Electrical Engineering-Systems University of Southern California
This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processo... 详细信息
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Implementation of linear algebra algorithms in FPGA-based rational fraction arithmetic units
Implementation of linear algebra algorithms in FPGA-based ra...
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9th International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics
作者: Maslennikow, Oleg Ratusmiak, Piotr Sergyienko, Anatoli Tech Univ Koszalin Dept Elect Ul Sniadeckich 2 PL-75453 Koszalin Poland Natl Tech Univ Kiev Ukraine
In this paper, two fixed size processor array architectures, which are destined for realization of several linear algebra algorithms, are proposed. In order to implementation of these architecture in modern FPGA devic... 详细信息
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Implementation of Cholesky LLT-decomposition algorithm in FPGA-based rational fraction parallel processor
Implementation of Cholesky LL<SUP>T</SUP>-decomposition algo...
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14th International Conference on Mixed Design of Integrated Circuits and Systems
作者: Maslennikow, O. Ratuszniak, P. Sergyienko, A. Tech Univ Koszalin Dept Elect & Comp Sci PL-75453 Koszalin Poland
In this paper, the fixed size processor array architecture, which is destined for realization of LLT-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to impl... 详细信息
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