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vlsi architecture of arithmetic coder Used in SPIHT

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2012年第4期20卷 697-710页

作者： Liu, Kai Belyaev, Evgeniy Guo, Jie Xidian Univ Comp Sch Xian 710071 Shaanxi Peoples R China Russian Acad Sci St Petersburg Inst Informat & Automat St Petersburg 199178 Russia Xidian Univ Commun Sch Xian 710071 Shaanxi Peoples R China

A high-throughput memory-efficient arithmetic coder architecture for the set partitioning in hierarchical trees (SPIHT) image compression is proposed based on a simple context model in this paper. The architecture benefits from various optimizations performed at different levels of arithmetic coding from higher algorithm abstraction to lower circuits' implementations. First, the complex context model used by software is mitigated by designing a simple context model, which just uses the brother nodes' states in the coding zerotree of SPIHT to form context symbols for the arithmetic coding. The simple context model results in a regular access pattern during reading the wavelet transform coefficients, which is convenient to the hardware implementation, but at a cost of slight performance loss. Second, in order to avoid rescanning the wavelet transform coefficients, a breadth first search SPIHT without lists algorithm is used instead of SPIHT with lists algorithm. Especially, the coding bit-planes of each zero tree are processed in parallel. Third, an out-of-order execution mechanism for different types of context is proposed that can allocate the context symbol to the idle arithmetic coding core with a different order that of the input. For the balance of the input rate of the wavelet coefficients, eight arithmetic coders are replicated in the compression system. And in one arithmetic coder, there exists four cores to process different contexts. Fourth, several dedicated circuits are designed to further improve the throughput of the architecture. The common bit detection (CBD) circuit is used for unrolling the renormalization stage of the arithmetic coding. The carry look-ahead adder (CLA) and fast multiplier-divider are also employed to shorten the critical path in the architecture. Moreover, an adaptive clock switch mechanism can stop some invalid bit-planes' clock for the power saving purpose according to the input images. Experimental results demonstrate that the p

关键词： arithmetic coding common bit detection (CBD) circuit context model out-of-order execution set partitioning in hierarchical trees (SPIHT) vlsi arithmetic coder architecture

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