检索结果-内蒙古大学图书馆

variable block size motion estimation Architecture with a Fast Bottom-Up Decision Mode and an Integrated motion Compensation Targeting the H.264/AVC Video Coding Standard 10

Variable Block Size Motion Estimation Architecture with a Fa...

引用

23rd Symposium on Integrated Circuits and Systems Design

作者： Dornelles, Robson S. S. Sampaio, Felipe M. Agostini, Luciano V. Fed Univ Pelotas UFPel Grp Architectures & Integrated Circuits GACI Pelotas RS Brazil

ISBN: (纸本)9781450302883

This work presents a new algorithm for the H.264/AVC variable block size motion estimation (VBSME) Decision Mode, which uses a bottom-up approach to merge the 4x4 motion vectors into larger-block predicted vectors. This work also presents a low cost architecture for the VBSME with an Integrated motion Compensation that implements our decision mode algorithm. This architecture reduces the number of accesses to the encoder main memory, since the motion Compensation module does not access the main memory in our solution. The architecture also presents the best trade-off between cost and throughput among the related works. This is important since this is a simplified low cost solution for the Inter Frame prediction, the most complex hardware module of the H.264/AVC video encoder.

关键词： H.264/AVC video coding variable block size motion estimation motion Compensation Bottom-Up Decision Mode

来源：评论

学校读者我要写书评

暂无评论

Effective Search Point Reduction Algorithm and Its VLSI Design for HDTV H.264/AVC variable block size motion estimation

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2012年第7期22卷 981-988页

作者： Tsai, An-Chao Bharanitharan, K. Wang, Jhing-Fa Lee, Kuan-I Natl Cheng Kung Univ Dept Elect Engn Tainan 701 Taiwan

variable block size motion estimation (VBSME) in H.264/AVC has greatly led to achieve an optimal inter frame encoding. However, the computation burden of the VBSME becomes the bottleneck of the H.264/AVC encoders. The conventional architecture in hardware realization is hard to adopt a fast software algorithm suitable to reduce the VBSME computation burden. Therefore, this paper presents a search point reduction (SPR) algorithm with an efficient hardware design, able to decrease the motion estimation time while maintaining the coding performance of H.264. The effectiveness of the proposed method is compared with those of existing methods with respect to chip area, operation frequency, and throughput rate. The proposed SPR algorithm increases the coding speed by around 90%;with a peak signal-to-noise ratio drop of less than 0.1 dB than that achieved by the JM reference software. The proposed SPR algorithm can operate at 200MHz with 191 k gate count, which supports high-definition television 1280 x 720 format.

关键词： 2-D systolic array H.264/AVC variable block size motion estimation

来源：评论

学校读者我要写书评

暂无评论

Algorithm and software optimization of variable block size motion estimation for H.264/AVC on a VLIW-SIMD DSP

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第3期51卷 289-302页

作者： Lee, Wonchul Choi, Hyojin Sung, Wonyong Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea

We implemented the H.264/AVC variable block size motion estimation (VBSME) using a very long instruction word (VLIW)-single instruction multiple data (SIMD) digital signal processor (DSP). The SAD_Reuse method which has a regular structure is chosen for VBSME not only to remove redundant sum of absolute difference (SAD) operations but also to utilize the instruction level parallelism (ILP) and data level parallelism (DLP) of the architecture. A fast mode decision algorithm is developed to reduce the number of 'compare and update' operations and simplify the rate distortion optimization (RDO). The developed fast mode decision uses the difference of motion vectors and the maximum a posteriori (MAP) estimation of the rate-distortion costs. Several advanced software techniques that include software pipelining and packed-data processing are employed. Especially, memory access overhead reduction schemes including the multi-block processing and the inter-procedural scheduling are used for the software optimization. In order to reduce the 'write buffer full' in the quarter pixel ME, a 4 bit quantization scheme is developed, which increases the number of arithmetic operations but decreases the stall cycles very much. The implemented variable block size ME for H.264/AVC requires an average of 9 M and 78 Mcycles per frame for QCIF and CIF size video sequences, respectively, in the TMS320C64x DSP architecture.

关键词： variable block size motion estimation H.264/AVC encoder VLIW (very long instruction word) SIMD (single instruction multiple data)

来源：评论

学校读者我要写书评

暂无评论

HIERARCHICAL variable block size motion estimation TECHNIQUE FOR motion SEQUENCE CODING

引用

OPTICAL ENGINEERING 1994年第8期33卷 2553-2561页

作者： KIM, JW LEE, SU AUTOMAT & SYST RES INST SEOUL 151742SOUTH KOREA

motion-compensated coding, which exploits the temporal redundancies in the moving images, is one of the most popular techniques currently used. Recently, a variable block size (VBS) motion estimation technique has been proposed to improve the performance of the motion-compensated transform coding (MCTC). This technique allows larger blocks to be used when smaller blocks provide little gain, saving the bit rates especially for areas containing more complex motion. However, there have been few efforts to investigate an efficient VBS motion structure for reducing the motion vector coding rates further. Hence, a new VBS motion estimation technique based on a hierarchical structure is proposed that improves the motion vector encoding efficiency and reduces the number of motion vectors to be transmitted as well. Specifically, the gain/cost motion estimation technique with the selective motion prediction is utilized for the topmost level motion vector search, exploiting the redundancies among the neighboring motion vectors. Also, a restricted search with respect to the topmost level motion vector enables more flexible and efficient motion vector encoding for the remaining lower level blocks. Intensive simulations on several moving image sequences show that the MCTC employing the VBS motion estimation provides a performance improvement of 0.7 to 1.0 dB, in terms of peak SNR, compared with the fixed block size motion estimation.

关键词： motion COMPENSATED CODING variable block size motion estimation HIERARCHICAL variable block size block MATCHING ALGORITHM motion VECTOR CODING

来源：评论

学校读者我要写书评

暂无评论

Fast variable block size motion estimation by adaptive early termination

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2006年第8期16卷 1021-1026页

作者： Al Qaralleh, Esam A. Chang, Tian-Sheuan Natl Chiao Tung Univ Dept Elect Engn Hsinchu 160 Taiwan

This paper presents a fast motion estimation algorithm by adaptively changing the early termination threshold for the current accumulated partial sum of absolute difference (SAD) value. The simulation results show that the proposed algorithm can provide the similar quality while saving 77.9% and 50.6% of SAD computation when comparing with early termination methods in MPEG-4 VM18.0 and H.264 JM9.0, respectively.

关键词： early termination H.264 MPEG-4 variable block size motion estimation

来源：评论

学校读者我要写书评

暂无评论

Architecture design of variable block size motion estimation for full and fast search algorithms in H.264/AVC

引用

COMPUTERS & ELECTRICAL ENGINEERING 2011年第3期37卷 285-299页

作者： Xiong, Xuanxing Song, Yang Akoglu, Ali Univ Arizona Dept Elect & Comp Engn Reconfigurable Comp Lab Tucson AZ 85721 USA

Fast search algorithms (FSA) used for variable block size motion estimation follow irregular search (data access) patterns. This poses as the main challenge in designing hardware architectures for them. In this study, we build a baseline architecture for fast search algorithms using state-of-the-art components available in academia. We improve its performance by introducing: (1) a super 2-dimensional (2-D) random access memory architecture for reading regular and interleaved two-rows or two-columns as opposed to one-row or one-column accessibility of the state of the art;(2) a 2-D processing element array with a tuned interconnect to support neighborhood connections required by the conventional fast search algorithms and to exploit on-chip data reuse. Results show that our design increases system throughput by up to 85.47%, and achieves power reduction by up to 13.83% with an area increase in the worst case by up to 65.53% compared to the baseline architecture. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： ARCHITECTURE variable block size motion estimation SEARCHING ALGORITHM Fasting Building design

来源：评论

学校读者我要写书评

暂无评论

A low-power VLSI implementation for fast full-search variable block size motion estimation

引用

INTERNATIONAL JOURNAL OF ELECTRONICS 2013年第9期100卷 1240-1255页

作者： Li, Peng Tang, Hua Univ Minnesota Dept Elect & Comp Engn Duluth MN 55812 USA

variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This article presents a low-power VLSI implementation for VBSME, which employs a fast full-search block-matching algorithm to reduce power consumption, while preserving the optimal motion vectors (MVs). The fast full-search algorithm is based on the comparison of the current minimum sum of absolute difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally determine the specific conservative lower bound of SAD and then implement the fast full-search algorithm in FPGA and 0.18 mu m CMOS technology. To the best of our knowledge, this is the first time that a fast full-search block-matching algorithm is explored to reduce power consumption in the context of VBSME and implemented in hardware. Experiment results show that the proposed design can save power consumption by 45% compared to conventional VBSME designs that give optimal MV based on the full-search algorithms.

关键词： H. 264/AVC variable block size motion estimation fast full-search block-matching low-power design

来源：评论

学校读者我要写书评

暂无评论

Bit Plane Matching Based variable block size motion estimation Method and Its Hardware Architecture

引用

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2010年第3期56卷 1625-1633页

作者： Celebi, Anil Lee, Hyuk-Jae Ertuerk, Sarp Kocaeli Univ Dept Elect & Telecommun Engn Kocaeli Univ Lab Image & Signal Proc KULIS TR-41380 Kocaeli Turkey Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151 South Korea Seoul Natl Univ Dept Elect Engn Seoul 151 South Korea

variable block size motion estimation (VBSME) is one of the most important features of state-of-the-art video encoders. In the H.264/AVC encoder, the computational complexity of integer motion estimation is about 75%. Therefore, reducing this complexity is one of the key points to provide low power video encoding. In this paper, a reconfigurable bit plane matching based VBSME method and a runtime reconfigurable hardware architecture are proposed to allow low-power consumer electronic devices to make a trade-off between power requirements and motion estimation (ME) accuracy. The proposed ME method is the only low complexity ME algorithm proposed in the literature so far that can provide compatible ME accuracy for lower block sizes compared to the sum of absolute difference (SAD) criterion. A new data path for the computation of the matching criterion in the proposed hardware architecture which has a fully arithmetic structure is proposed to improve the previously utilized LUT based architectures by having a fully arithmetic structure(1).

关键词： Bit plane matching gray coding variable block size motion estimation reconfigurable hardware architecture

来源：评论

学校读者我要写书评

暂无评论

An efficient VLSI architecture for H.264 variable block size motion estimation

引用

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2005年第4期51卷 1291-1299页

作者： Ou, CM Le, CF Hwang, WJ Ching Yun Univ Dept Elect Engn Chungli 320 Taiwan Natl Taiwan Normal Univ Grad Inst Comp Sci & Informat Engn Taipei 117 Taiwan

This paper proposes a novel flexible VLSI architecture for the implementation of variable block size motion estimation (VBSME). The architecture is able to perform a full motion search on integral multiples of 4x4 blocks sizes. To use the architecture, each 16x16 macroblock of the source frames should be partitioned into sixteen 4x4 non-overlapping subblocks, called primitive subblocks. The architecture contains sixteen modules and one VBSME processor. Each module, realized by cascading ID systolic arrays, is responsible for the block-matching operations of a different primitive subblock The realization has the, advantages of high throughput, high flexibility and 100 % processing element (PE) utilization. The motion estimation of all the primitive subblocks are performed in parallel. Because these primitive subblocks can be used to form the 41 subblocks of different sizes specified by the H.264, the VBSME processor is employed to concurrently compute the sums of absolute differences (SADs) of all the 41 subblocks from the SADs of the primitive subblocks. This new architecture has lower latency and higher throughput over other exiting VBSME architectures for the hardware implementation of H.264 encoders(1).

关键词： video coding VLSI architecture variable block size motion estimation H.264 standard

来源：评论

学校读者我要写书评

暂无评论

Hardware-Efficient Propagate Partial SAD Architecture for variable block size motion estimation in H.264/AVC

Hardware-Efficient Propagate Partial SAD Architecture for Va...

引用

17th Great Lakes Symposium on VLSI

作者： Liu, Zhenyu Huang, Yiqing Song, Yang Goto, Satoshi Ikenaga, Takeshi Waseda Univ IPS Kitakyushu Fukuoka 8080135 Japan

ISBN: (纸本)9781595936059

One hardware efficient and high speed architecture for variable block size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing the processing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18 mu m CMOS 1P6M standard cell library, the maximum clock speed of this design is 227MHz in worst work conditions (1.62V, 125 degrees C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

关键词： H.264 variable block size motion estimation VLSI

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：