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A ONE-SIDED JACOBI ALGORITHM FOR computing THE SINGULAR VALUE DECOMPOSITION ON A vector COMPUTER

SIAM JOURNAL ON SCIENTIFIC AND STATISTICAL computing 1989年第2期10卷 359-371页

作者： DERIJK, PPM

An old algorithm for computing the singular value decomposition, which was first mentioned by Hestenes [SIAM J. Appl. Math., 6 (1958), pp. 51–90], has gained renewed interest because of its properties of parallelism and vectorizability. Some computational modifications are given and a comparison with the well-known Golub–Reinsch algorithm is made. Comparative experiments on a CYBER 205 are reported.

关键词： 65F15 65F20 65F25 15A18 singular value decomposition one-sided Jacobi algorithm vector computing

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SOLVING LINEAR-SYSTEMS ON A vector COMPUTER

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 1987年第3期18卷 353-367页

作者： HOFFMANN, W UNIV AMSTERDAM INST MATH1018 WB AMSTERDAMNETHERLANDS

This paper gives a classification for the triangular factorization of square matrices. These factorizations are used for solving linear systems. Efficient algorithms for vector computers are presented on basis of criteria for optimal algorithms. Moreover, the Gauss—Jordan elimination algorithm in a version which admits efficient implementation on a vector computer is described. Comparative experiments in FORTRAN 77 with FORTRAN 200 extensions for the Cyber 205 are reported.

关键词： Gaussian elimination LU-decomposition Gauss—Jordan algorithm linear equations vector computing

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SOLVING 3D BLOCK BIDIAGONAL LINEAR-SYSTEMS ON vector COMPUTERS

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 1989年第1-2期27卷 323-330页

作者： SCHLICHTING, JJFM VANDERVORST, HA CONTROL DATA BV 2285 VL RIJSWIJKNETHERLANDS DELFT UNIV TECHNOL FAC TECH MATH & INFORMAT2600 AJ DELFTNETHERLANDS

Standard 7-point finite-difference discretization of second-order PDEs over a rectangular grid over a 3-dimensional block leads, with the usual lexicograpical ordering of the gridpoints, to block tridiagonal linear systems. In many popular iterative methods for the solution of these systems, triangular systems which have a block bidiagonal structure have to be solved. This is often recognized to be the major bottleneck, on vector computers, with respect to the computational speed, when carried out in a straightforward manner. In this paper we will discuss different techniques for the vectorization of the solution of 3D-block bidiagonal systems. We will report on actually observed performances for the ICCG algorithm, for which these bidiagonal systems have the reputation to spoil the overall performance, on some computers. The potentially most powerful of the vectorization techniques leads to long vector operations, at the cost, however, of strides and indirect addressing. Since the CYBER 205 is generally believed to stay behind in performance under such circumstances, we have chosen this machine to show in detail how these vectorization techniques can be implemented with almost equal performance as in the same contiguous vector case. Our methods are directly applicable to the ETA-10 family of supercomputers and may be adapted to other vector computers as well.

关键词： vectorized ILU-preconditioning block bidiagonal matrices linear recurrence relations vector computing hyperplane ordering ICCG

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VIA: A Smart Scratchpad for vector Units with Application to Sparse Matrix Computations 27

VIA: A Smart Scratchpad for Vector Units with Application to...

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27th IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Pavon, Julian Valdivieso, Ivan Vargas Barredo, Adrian Marimon, Joan Moreto, Miquel Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665422352

Sparse matrix operations are critical kernels in multiple application domains such as High Performance computing, artificial intelligence and big data. vector processing is widely used to improve performance on mathematical kernels with dense matrices. Unfortunately, existing vector architectures do not cope well with sparse matrix computations, achieving much lower performance in comparison with their dense counterparts. To overcome this limitation, we present the vector Indexed Architecture (VIA), a novel hardware vector architecture that accelerates applications with irregular memory access patterns such as sparse matrix computations. There are two main bottlenecks when computing with sparse matrices: irregular memory accesses and index matching. VIA addresses these two bottlenecks with a smart scratchpad that is tightly coupled to the vector Functional Units within the core. Thanks to this structure, VIA improves locality for sparse-dense computations and improves the index matching search process for sparse computations. As a result, VIA achieves significant performance speedup over highly optimized state-of-the-art C++ algebra libraries. On average, VIA outperforms sparse matrix vector multiplication, sparse matrix addition and sparse matrix matrix multiplication kernels by 4.22 x, 6.14x and 6.00 x, respectively, when evaluated over a thousand sparse matrices that arise in real applications. In addition, we prove the generality of VIA by showing that it can accelerate histogram and stencil applications by 4.5x and 3.5x, respectively.

关键词： Sparse Algebra vector computing Scratchpad Memory

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Optimizations of a Linear Matrix Solver in a Composite Simulation for a vector Computer 12

Optimizations of a Linear Matrix Solver in a Composite Simul...

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12th International Symposium on Parallel Architectures, Algorithms and Programming (PAAP)

作者： He, Zhilin Komatsu, Kazuhiko Sato, Masayuki Kobayashi, Hiroaki Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan Tohoku Univ Cybersci Ctr Sendai Miyagi Japan

ISBN: (纸本)9781665496391

A fiber-reinforced composite simulation based on a spring-element model can capture the stress field of composites. Since the simulation can calculate the maximum stress to composites, it is essential to discover a more reliable composite structure, and the acceleration of the simulation is required. However, a linear matrix solver in the simulation needs a long execution time and a vast memory bandwidth to solve element displacements of the structure, especially for large-scale composites. To accelerate the simulation, this paper proposes a vectorization method of a linear matrix solver on a vector computer. By applying loop optimizations such as splitting, unrolling, distribution, and interchange, efficient vector computing is realized. From the performance evaluation, it is shown that the optimizations achieve more than 15.5x speedups on the vector computer. Furthermore, the optimized simulation on a vector computer achieves a 2.4x to 3.7x speedup compared with the original version on the Intel Xeon.

关键词： vector computing Linear matrix solvers Composite simulations

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VAQUERO: A Scratchpad-based vector Accelerator for Query Processing 29

VAQUERO: A Scratchpad-based Vector Accelerator for Query Pro...

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29th IEEE International Symposium on High-Performance Computer Architecture (HPCA)

作者： Pavon, Julian Vargas Valdivieso, Ivan Marimon, Joan Figueras, Roger Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665476522

Database Management Systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centers. There have been many efforts to accelerate DBMS application performance. One of the most explored techniques is the use of vector processing. Unfortunately, conventional vector architectures have not been able to exploit the full potential of DBMS acceleration. In this paper, we present VAQUERO, our Scratchpad-based vector Accelerator for QUEry pROcessing. VAQUERO improves the efficiency of vector architectures for DBMS operations such as data aggregation and hash joins featuring lookup tables. Lookup tables are significant contributors to the performance bottlenecks in DBMS processing suffering from insufficient ISA support in the form of scatter-gather instructions. VAQUERO introduces a novel Advanced Scratchpad Memory specifically designed with two mapping modes - direct- and associative-mode. These mapping modes enable VAQUERO to accelerate real-world databases with workload sizes that significantly exceed the scratchpad memory capacity. Additionally, the associative-mode allows to use VAQUERO with DBMS operators that use hashed keys, e.g. hash-join and hash-aggregate. VAQUERO has been designed considering general DBMS algorithm requirements instead of being based on a particular database organization. For this reason, VAQUERO is capable to accelerate DBMS operators for both row- and column-oriented databases. In this paper, we evaluate the efficiency of VAQUERO using two highly optimized popular open-source DBMS, namely the row-based PostgreSQL and column-based MonetDB. We implemented VAQUERO at the RTL level and prototype it, by performing Place&Route, at the 7nm technology node. VAQUERO incurs a modest 0.15% area overhead compared with an Intel Ice Lake processor. Our evaluation shows that VAQUERO significantly outperforms PostgreSQL and MonetDB by 2.09x and 3.32x respectively, when processing operators and queries

关键词： vector computing Scratchpad Memory Database Accelerator PostgreSQL MonetDB

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vector-Deductive Memory-Based Transactions for Fault-As-Address Simulation 12

Vector-Deductive Memory-Based Transactions for Fault-As-Addr...

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12th IEEE International Scientific Technical Conference on Dependable Systems, Services and Technologies (DESSERT) - Dependable and Trustworthy AI, IoE, Big Data Analytics for a Safe and Secure World

作者： Devadze, David Davitadze, Zaza Hahanova, Anna Batumi Shota Rustaveli State Univ Dept Comp Sci Batumi Georgia Kharkiv Natl Univ Radio Elect Design Automat Dept Kharkiv Ukraine

ISBN: (纸本)9798350333046

The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. A metric-axiom of convolutional closure of cyclic distances between n objects into the 0-space is introduced. A model of xor-relations between wonderful logical functions (and circle plus or circle plus xor = 0) of digital circuits is proposed;it is convoluted into zero-space, which makes it possible to solve problems of technical diagnosis, generative machine learning, similarity-difference search between processes and phenomena. A failure-driven management metric T circle plus F circle plus L = 0 is introduced, which formalizes all known processes for creating computing, including design and test, cyber-physical and cyber-social computing, federated and generative ML-computing. The equation of logical analysis is introduced S circle plus D - a boolean OR b = U, which makes it possible to calculate the similarity-difference between objects by means of parallel logical procedures on binary vectors that form the U-universe. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expre

关键词： vector computing vector form of logic matrix of deductive vectors table of synthesis of deductive vectors analytical form of structures deductive-vector method of fault analysis digital circuit vector model of defects functions and structures sequencer of vector deductive fault simulation

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Mapping Irregular Computations for Molecular Docking to the SX-Aurora TSUBASA vector Engine

Mapping Irregular Computations for Molecular Docking to the ...

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11th IEEE/ACM Workshop on Irregular Applications - Architectures and Algorithms (IA3)

作者： Solis-Vasquez, Leonardo Focht, Erich Koch, Andreas Tech Univ Darmstadt Darmstadt Germany NEC Deutschland GmbH Stuttgart Germany

ISBN: (纸本)9781665411264

Molecular docking is a key method in computer-aided drug design, where the rapid identification of drug candidates is crucial for combating diseases. AutoDock is a widely-used molecular docking program, having an irregular structure characterized by a divergent control flow and compute-intensive calculations. This work investigates porting AutoDock to the SX-Aurora TSUBASA vector engine and evaluates the achievable performance on a number of real-world input compounds. In particular, we discuss the platform-specific coding styles required to handle the high degree of irregularity in both local-search methods employed by AutoDock. These Solis-Wets and ADADELTA methods take up a large part of the total computation time. Based on our experiments, we achieved runtimes on the SX-Aurora TSUBASA VE 20B that are on average 3x faster than on modern dual-socket 64-core CPU nodes. Our solution is competitive with V100 GPUs, even though these already use newer chip fabrication technology (12 nm vs. 16 nm on the VE 20B).

关键词： variable execution performance divergent control structures molecular docking AutoDock vector computing SX-Aurora TSUBASA

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ADVANCED ARRAY OPTIMIZATIONS FOR HIGH-PERFORMANCE FUNCTIONAL LANGUAGES

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1995年第3期6卷 229-239页

作者： CANN, DC EVRIPIDOU, P SO METHODIST UNIV DEPT COMP SCI & ENGNDALLASTX 75275

In this paper, we discuss and evaluate three optimizations for reducing memory management overhead and data copying costs in SISAL 1.2 programs that build arrays. The first, called framework preconstruction, eliminates superfluous allocate-deallocate sequences in cyclic computations. The second, called aggregate storage subsumption, reduces the management overhead for compound array components. The third, called predictive storage preallocation, eliminates superfluous data copying in filtered array constructions and simplifies their parallelization. We have added all three optimizations to the Optimizing SISAL Compiler with rewarding improvements in SISAL program performance on vector-parallel machines such as those built by Gray Computer Corporation, Convex, and Gray Research.

关键词： FUNCTIONAL LANGUAGES PARALLEL computing vector computing IMPERATIVE LANGUAGES COPY ELIMINATION STORAGE OPTIMIZATIONS ARRAYS

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Stability of the Gauss-Huard algorithm with partial pivoting

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computing 1997年第3期58卷 225-244页

作者： Dekker, TJ Hoffmann, W Potma, K Department of Computer Systems SJ Amsterdam

This paper considers elimination methods to solve dense linear systems, in particular a variant of Gaussian elimination due to Huard [13]. This variant reduces the system to an equivalent diagonal system just like Gauss-Jordan elimination, but does not require more floating-point operations than Gaussian elimination. To preserve stability, a pivoting strategy using column interchanges, proposed by Hoffmann [10], is incorporated in the original algorithm. An error analysis is given showing that Huard's elimination method is as stable as Gauss-Jordan elimination with the appropriate pivoting strategy. This result is proven in a similar way as the proof of stability for Gauss-Jordan elimination given in [4]. Numerical experiments are reported which verify the theoretical error analysis of the Gauss-Huard algorithm.

关键词： Gaussian elimination Gauss-Jordan elimination linear systems LU factorization pivoting strategies parallel algorithms vector computing

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