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MPEG2 video decoder and AC-3 audio decoder LSIs for DVD player

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 1997年第3期43卷 462-468页

作者： Yasuda, M Nishio, T Toyokura, M Kawamura, A Fujiwara, M Akiyama, T MATSUSHITA ELECT IND CO LTD SEMICOND RES CTROSAKAJAPAN MATSUSHITA ELECT IND CO LTD MULTIMEDIA DEV CTROSAKAJAPAN MATSUSHITA ELECT CORP LSI DEV CTROSAKAJAPAN

We have developed the MPEG2 video decoder and the AC-3 audio decoder LSIs for the DVD player. These decoder LSIs together with single 16Mbits SDRAM and D/A converters realize the audio/video processing unit with-the small number of components for the DVD player. The video decoder LSI adopts the RISC controller to control the dedicated processing hardware cores and a design to integrate the frame memory and bitstream buffers into single external memory. The audio decoder LSI adopts the 24bits fixed point DSP core and the dedicated AC-3 accelerator circuit and so on to reduce the software processing amount in AC-3 audio decoding.

关键词： Dolby AC-3 decoders 24-bit SMALL COMPONENT frame memory software process improvement Audio Large scale integrate circuit video decoder

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A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile video decoder Chip

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2011年第4期46卷 777-788页

作者： Zhou, Dajiang Zhou, Jinjia He, Xun Zhu, Jiayi Kong, Ji Liu, Peilin Goto, Satoshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan Shanghai Jiao Tong Univ Dept Elect Engn Shanghai 200030 Peoples R China

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096x2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

关键词： DRAM bandwidth embedded compression frame recompression H.264/AVC QFHD ultra high definition video decoder

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NTSC/PAL/SECAM digital video decoder with high-precision resamplers

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2005年第1期51卷 287-294页

作者： Suzuki, Y Gai, T Yamakawa, M Sugiura, H Mitsubishi Electr Corp Adv Technol R&D Ctr Kyoto 6178550 Japan

This paper presents architecture of an all-digital multistandard video decoder that uses a single crystal oscillator of fixed frequency. The proposed digital video decoder requires no analog component and is based on a fully synchronous design. Resampling schemes that create line-locked sampling and hurst-locked sampling are described. Phase jitter of 1 ns or less is achieved using 27 MHz clock, and 3-D (3-dimensional) Y/C separation becomes feasible in the free-running clock system. High-precision digital phase-locked loops and fractional delay filters implement resampling of video data, which eliminate the need,for analog PLLs that generate clocks locked to input video(1).

关键词： digital PLL fractional delay filter resampling video decoder

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Flexible Multi-Core Platform for a Multiple-Format video decoder

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND video TECHNOLOGY 2015年第2期80卷 163-179页

作者： Jo, Hyun-Ho Ahn, Yong-Jo Kang, Dae-Beom Ji, Bongil Sim, Dong-Gyu Lee, Jae-Jin Kwangwoon Univ Image Proc Syst Lab Seoul 139701 South Korea Elect & Telecommun Res Inst Multimedia Processor Res Sect Taejon 305700 South Korea

This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2x in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56x in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60 MHz.

关键词： Multi-codec video decoder ASIP Multi-core platform

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Implementation of the AVS video decoder on a Heterogeneous Dual-Core SIMD Processor

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2011年第2期57卷 673-681页

作者： Koziri, Maria Zacharis, Dimitrios Katsavounidis, Ioannis Bellas, Nikos Univ Thessaly Dept Comp & Commun Engn Volos 38221 Greece

Multi-core Application Specific Instruction Processors (ASIPs) are increasingly used in multimedia applications due to their high performance and programmability. Nonetheless, their efficient use requires extensive modifications to the initial code in order to exploit the features of the underlying architecture. In this paper, through the example of implementing Advance video Coding (AVS) to a heterogeneous dual-core SIMD processor, we present a guide to developers who wish to perform task-level decomposition of any video decoder in a multi-core SIMD system. Through the process of mapping AVS video decoder to a dual-core SIMD processor we aim to explore the different forms of parallelism inherent in a video application and exploit to speed-up AVS decoding in order to achieve real time functionality. Simulation results showed that the extraction of parallelism at all levels of granularity, especially at the higher levels, can give a total speed-up of more than 195x compared to a software x86-based implementation, which enables real-time, 25fps decoding of D1 video(1).

关键词： AVS video decoder SIMD processor multi core processor

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Cache modeling and optimization for portable devices running MPEG-4 video decoder

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MULTIMEDIA TOOLS AND APPLICATIONS 2006年第2期28卷 239-256页

作者： Asaduzzaman, Abu Mahgoub, Imad Florida Atlantic Univ Dept Comp Sci & Engn Boca Raton FL 33431 USA

There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is an important and demanding multimedia application. To satisfy the growing consumer demands, more functions are added to support MPEG-4 video applications. With improved CPU speed, memory sub-system deficiency is the major barrier to improving the system performance. Studies show that there is Sufficient reuse of values for caching that significantly reduce the memory bandwidth requirement for video data. Software decoding of MPEG-4 video data generates Much more cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is cache modeling and optimization for portable Communication devices running MPEG-4 video decoding algorithm. The architecture we Simulate includes a digital signal processor (DSP) for running the MPEG-4 decoding algorithm and a memory system with two levels of caches. We use VisualSim and Cachegrind Simulation tools to optimize cache sizes, levels of associativity, and cache levels for a portable device decoding MPEG-4 video.

关键词： cache modeling cache optimization portable devices MPEG-4 video decoder

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Architecture and bus-arbitration schemes for MPEG-2 video decoder

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR video TECHNOLOGY 1999年第5期9卷 727-736页

作者： Li, JH Ling, N Santa Clara Univ Dept Comp Engn Santa Clara CA 95053 USA

An efficient MPEG-2 video decoder architecture together with several effective bus-arbitration schemes designed to meet the main profile at main level (MP@ML) real-time decoding requirement is presented in this paper, The overall architecture, as well as the design of major function-specific processing blocks (variable-length decoder, inverse two-dimensional discrete cosine transform unit, and motion-compensation unit), is discussed. A hierarchical and distributed controller approach is used, a bus-monitoring model for different bus-arbitration schemes to control external DRAM accesses is developed, and the system is simulated. Practical issues and buffer sizes are addressed and evaluated. With a 27-MHz clock, our architecture uses many :fewer than the 667 cycles, the upper bound for the MP@ML decoding requirement, to decode each macroblock with a single external bus and DRAM.

关键词： bus arbitration MPEG-2 video decoder

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A 600 mW single chip MPEG2 video decoder

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IEICE TRANSACTIONS ON ELECTRONICS 1995年第12期E78C卷 1691-1696页

作者： Miura, K Koyanagi, H Sumihiro, H Emoto, S Ozaki, N Ishikawa, T Sony Corp Atsugi-shi Japan

This paper describes a 600 mW single-chip MPEG2 video decoder, implemented in a 0.5 mu m triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode the Main profile at Main level of MPEG2 bit streams.

关键词： MPEG2 video decoder low power dual-port RAM multiple-clock asynchoronization

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A Frame-Parallel 2 Gpixel/s video decoder Chip for UHDTV and 3-DTV/FTV Applications

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第12期23卷 2768-2781页

作者： Zhou, Jinjia Zhou, Dajiang Zhu, Jiayi Goto, Satoshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan

The first single-chip design that supports real-time H.264/Advanced video Coding decoding of 8k (7680 x 4320) 60 frames/s is realized. It also supports multiview decoding for up to 32 720p views or 16 1080p views. To significantly improve the throughput and reduce the memory bandwidth requirement, frame-level parallelism is exploited for the proposed design. First, a frame dependency protection scheme enables frame-parallel decoding, by reusing multiple replicas of an existing design. This results in a system throughput of 2 Gpixels/s, at least 3.75 times better than previous chips. Moreover, a reference window synchronization scheme and a 2-level hybrid caching structure are proposed to achieve 44% memory bandwidth reduction of motion compensation, by utilizing frame-level data reuse. The bandwidth reduction results in 22% Dynamic Random-Access Memory power saving of the whole decoder.

关键词： 3-D TV application-specified integrated circuit (ASIC) H.264/Advanced video Coding Super High Version ultrahigh definition television (UHDTV) video decoder VLSI

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An H.264 video decoder Based on a Latest Generation DSP

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2009年第1期55卷 205-212页

作者： Pescador, F. Maturana, G. Garrido, M. J. Juarez, E. Sanz, C. Univ Politecn Madrid GDEM E-28040 Madrid Spain

Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed. Profiling tests have been carried out by using digital TV streams and DVD transcoded sequences. The speed of the new DSP running the decoder is 16% better than that of a forerunner with 20% more internal memory running the same decoder.(1)

关键词： H264 video decoder Software Optimization Latest Generation DSP

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