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ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 1995年第6期7卷 257-264页

作者： Tudor, PN Res. & Dev. Dept. BBC Tadworth UK

MPEG-2 is an extension of the MPEG-1 international standard for digital compression of audio and video signals. MPEG-1 was designed to code progressively scanned video at bit rates up to about 1.5 Mbit/s for applications such as CD-i (compact disc interactive). MPEG-2 is directed at broadcast formats at higher data rates;it provides extra algorithmic 'tools' for efficiently coding interlaced video, supports a wide range of bit rates and provides for multichannel surround sound coding. This tutorial paper introduces the principles used for compressing video according to the MPEG-2 standard, outlines the general structure of a video coder and decoder, and describes the subsets ('profiles') of the toolkit and the sets of constraints on parameter values ('levels') defined to date.

关键词： video codec video decoder video coder Codecs, coders and decoders video codecs Codes video signal compression television standards bit rates interlaced video coding digital compression compact disc interactive audio coding MPEG-2 standard MPEG-2 video compression SNR profiles parameter values Optical information, image and video signal processing audio signal compression 1.5 Mbit/s algorithmic tools Radio and television broadcasting MPEG-1 international standard multichannel surround sound coding video coding CD-I progressively scanned video

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VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR video TECHNOLOGY 2017年第2期27卷 380-393页

作者： Wang, Shihao Zhou, Dajiang Zhou, Jianbin Yoshimura, Takeshi Goto, Satoshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan

Ultrahigh definition television is becoming increasingly attractive and practical with the doubled compression performance delivered by High Efficiency video Coding (H.265/HEVC). Meanwhile, implementation of real-time video codecs is challenged by not only the huge throughput and memory bandwidth requirements but also the increased complexity of new algorithms. For motion compensation (MC) that is a known bottleneck in video decoding, the enlarged and diversified prediction unit sizes impose notably higher difficulties in trading off area, power, and memory traffic. This paper presents a very large scale integration implementation of HEVC MC that supports 7680 x 4320@60 frames/s bidirectional prediction. The MC design incorporates a highly efficient cache realized by novel architecture optimizations including distance biased directing mapping, eight-bank memory structure, row-based miss information compression, and mask-based block conflict checking. As a result, the proposed design not only achieves 8x throughput enhancement but also improves hardware efficiency by at least 2.01 times, in comparison with prior arts.

关键词： Cache H.264 H.265 High Efficiency video Coding (HEVC) interpolation motion compensation (MC) ultrahigh definition television (UHDTV) very large scale integration (VLSI) video decoder

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FPGA Implementation of a Full HD Real-time HEVC Main Profile decoder

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2014年第3期60卷 476-484页

作者： Engelhardt, Denis Moeller, Jan Hahlbeck, Jan Stabernack, Benno Heinrich Hertz Inst Nachrichtentech Berlin GmbH Fraunhofer Inst Telecommun Image Proc Dept D-10587 Berlin Germany

High Efficiency video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 % compared to H. 264/MPEG-4 AVC high profile, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications make implementing encoders and decoders a challenging task. A few software based implementations on DSPs and general purpose CPUs are known from the literature which suffer from real-time constraints, power dissipation and hardware costs of these systems. In this paper a pure hardware implementation of a Main Profile H. 265/MPEG-HEVC Full HD capable decoder is presented solving both real-time and power constraints respectively. As a first implementation approach a state-of-the-art FPGA technology is chosen as a prototyping platform. This design can be used as a starting point for an ASIC implementation(1).

关键词： HEVC video decoder FPGA hardware implementation

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A low-cost video frame-rate up conversion using compressed-domain information

A low-cost video frame-rate up conversion using compressed-d...

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Conference on Visual Communications and Image Processing 2005

作者： Sekiguchi, SI Idehara, Y Asai, K Mitsubishi Electr Corp Informat Technol R&D Ctr Kamakura Kanagawa Japan

ISBN: (纸本)0819459763

A new low-cost video frame-rate up conversion (FRC) technique that exploits compressed-domain information is proposed in this paper. Recent worldwide growth of digital video applications such as home AV network or mobile multimedia have been demanding higher video compression ratio in order to meet system requirements related to limited bandwidth or storage capacity. Enhancement of temporal resolution using FRC at decoder side is attractive in a sense that the R-D performance can be maintained even at low bitrate condition by dropping frames during encoding and recovering them at decoder side by FRC. The proposed FRC method aims to provide accurate estimates of block-based motion vectors for recovered frames based on compressed-domain information. The goal of our study is to realize a decoder design with robust FRC over a variety of implementation platforms from mobile to consumer set-top.

关键词： post processing frame-rate up conversion video decoder

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Low Complexity Implementation of Slim – HEVC decoder Design

Low Complexity Implementation of Slim – HEVC Decoder Design

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2016 IEEE Advanced Information Management,Communicates,Electronic and Automation Control Conference(IMCEC 2016)

作者： Jaehyuk So Kyungmook Oh Jaeseok Kim Department of Electrical and Electronic Engineering Yonsei University

ISBN: (纸本)9781509001668

High efficiency video Coding(HEVC) uses advanced compression techniques that H.264/AVC don't *** algorithmic techniques achieve about 50 percent of average bit-rate reduction compared to H.264/*** this paper,we present the low complexity HEVC decoder structure suitable for our HEVC *** proposed slim – HEVC decoder is compliant with HM 10.0 which is developed during standardization of *** decoder is composed of Contextbased adaptive binary arithmetic(CABAC),inverse quantization block,inverse transform block,Motion Compensation(MC),Deblocking Filter.

关键词： High Effiency video Coding(HEVC) video decoder Slim-HEVC

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Energy-aware Cache Assessment of HEVC Decoding

Energy-aware Cache Assessment of HEVC Decoding

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Monteiro, Eduarda Grellert, Mateus Bampi, Sergio Zatt, Bruno Fed Univ Rio Grande Sul UFRGS Grad Program Comp Sci PPGC Porto Alegre RS Brazil Fed Univ Pelotas UFPel Grad Program Comp Sci PPGC Pelotas Brazil

ISBN: (纸本)9781479953417

This paper presents a thorough analysis of energy consumption of a software HEVC decoder. The evaluation utilizes a framework developed herein specifically to estimate the energy consumption in all levels of cache hierarchies. Our framework is based on analytical models combined with memory profiling tools. Energy analyses of several cache hierarchies executing HEVC decoding with different input bit streams were carried out. Our results point to the most suited cache parameters for each video resolution. The energy was estimated for a 32nm CMOS technology. Our study includes different tradeoffs between energy efficiency and capacity, associativity, and main memory bandwidth. Our detailed analysis shows that the higher are the cache features, the more efficient is the energy consumption. The main memory bandwidth evaluation shows that the energy consumption increases with the main memory bandwidth requirement. Full HD video resolutions require up to 90 times higher bandwidth and 57 times more energy than class D resolutions.

关键词： HEVC energy cache memorry video decoder

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Context Adaptive Variable Length decoder of H.264

Context Adaptive Variable Length Decoder of H.264

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International Conference on Communication and Network Technologies (ICCNT)

作者： Yogesh, G. S. Ramachandran, S. Jawaharlal Nehru Technol Univ Hyderabad Andhra Prades India Natl Acad Excellence Bangalore Karnataka India

ISBN: (纸本)9781479962662

This paper presents a software implementation of context adaptive variable length decoder (CAVLD) and context adaptive variable length coder (CAVLC). Efficient algorithms for coding and decoding of Coeff_Token, levels, total zeros, and run_before have been developed, which are the five vital syntax elements of CAVLC and CAVLD. The necessary blocks namely Integer Transform, quantization and their inverses are also coded. This implementation can process video sequences of any size. Experiments have been conducted to process video sequences up to High Definition 720p (1280x720 pixels) resolution and up to 30fps frame rate and also for high resolution pictures. The reconstructed pictures are of acceptable video quality with PSNR values greater than 34dB. The design can be conFig. d to different Qp values. The proposed work is coded using matlab and serves as a basis for FPGA implementation of H.264 Base line video decoder.

关键词： CAVLC CAVLD VLC Quantization parameter video decoder

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Optimizing Off-Chip Memory Access Costs in Low Power MPEG-4 decoder 12

Optimizing Off-Chip Memory Access Costs in Low Power MPEG-4 ...

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3rd International Conference on Information and Communication Systems (ICICS)

作者： Habli, Haitham Ersfolk, Johan Lilius, Johan Westerlund, Tomi Nurmi, Jari Abo Akad Univ Dept Informat Technol Turku Finland Turku Univ Dept Informat Technol Turku Finland Tampere Univ Technol Dept Comp Syst Tampere Finland

ISBN: (纸本)9781450313278

One of the main sources for energy consumption in modern video coding algorithms is caused by reading reference frames from main memory. Once a reference frame block is in the local memory, we need to predict in advance when the same reference frame block would be reread from the main memory. The prediction relies on the calculation of motion vectors according to their absolute addresses. The reduction of the number of read accesses can be attained by calculating which motion vectors point to a part of the reference frame that can be copied to a local memory. This increases data locality, and thus reduces energy consumption. The optimized memory access algorithm was integrated into low power MPEG-4 decoder architecture [1, 2] and modeled using SystemC. A cycle accurate model simulation with optimized algorithm showed an average of 10% increase on runtime performance compared to an unoptimized typical video decoding algorithm.

关键词： Memory access fine-grained heterogeneous video decoder reusable data motion vector low power

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HIGH DEFINITION IEEE AVS decoder ON ARM NEON PLATFORM

HIGH DEFINITION IEEE AVS DECODER ON ARM NEON PLATFORM

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20th IEEE International Conference on Image Processing (ICIP)

作者： Wang, Ronggang Wan, Jie Wang, Wenmin Wang, Zhenyu Dong, Shengfu Gao, Wen Peking Univ Shenzhen Grad Sch Sch Elect & Comp Engn Beijing Peoples R China

ISBN: (纸本)9781479923410

Nowadays, mobile devices are capable of displaying video up to HD resolution. In this paper, we propose two acceleration strategies for Audio video coding Standard (AVS) software decoder on multi-core ARM NEON platform. Firstly, data level parallelism is utilized to effectively use the SIMD capability of NEON and key modules are redesigned to make them SIMD friendly. Secondly, a macroblock level wavefront parallelism is designed based on the decoding dependencies among macroblocks to utilize the processing capability of multiple cores. Experiment results show that AVS (IEEE 1857) HD video stream can be decoded in real-time by applying the proposed two acceleration strategies.

关键词： video decoder parallel decoding IEEE 1857 AVS ARM NEON SIMD

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LOW POWER DESIGN OF HIGH PERFORMANCE MEMORY ACCESS ARCHITECTURE FOR HDTV decoder

LOW POWER DESIGN OF HIGH PERFORMANCE MEMORY ACCESS ARCHITECT...

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IEEE International Conference on Multimedia and Expo (ICME 2007)

作者： Wang, Tsun-Hsien Chiu, Ching-Te Ind Technol Res Inst Informat & Commun Res Labs Hsinchu Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30013 Taiwan

ISBN: (纸本)9781424410163

To improve memory access efficiency and to reduce power consumption in HDTV video decoders, we propose a novel memory address mapping method and an efficient memory accessing architecture. The memory address mapping enables a computation-free memory address generation from the logical address of the data word in a video frame. The simple address generation is achieved by combining neighboring macroblocks into groups and stores the group of macroblocks in the same row of the external memory. By grouping suitable macroblocks, depending on interlaced or progressive scanning, we significantly reduce the cross-row memory accessing in the external memory, which is both time consuming and power consuming. In the memory accessing architecture, we rearrange the access order of luminance and chrominance data in motion compensations to further reduce the number of row changes of the external memory. Our analysis shows that the number of row changes is reduced by 87.67% and throughput of our memory-accessing scheme is improved by 30.91% compared to conventional approaches.

关键词： memory controller memory address mapping video decoder macroblock (MB)

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