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9th IEEE International Symposium on Embedded Multicore/Manycore Systems-on-Chip (MCSoC)

作者： Fathabadi, Asieh Salehi Maeda-Nunez, Luis Alfonso Butler, Michael J. Al-Hashimi, Bashir M. Merrett, Geoff V. Univ Southampton Elect & Comp Sci Southampton SO9 5NH Hants England

ISBN: (纸本)9781479986705

Run-Time Management (RTM) systems are used to control energy hooks at run-time to minimise the energy consumption of embedded systems with single and many-core processors. Typically, such RTM systems are aware of application requirements and utilise workload prediction and machine learning algorithms to estimate the optimal configuration. An RTM mechanism should not compromise the reliability or performance of the platform it is managing. Because of the potential complexity and interaction with the platform and its applications, we are using rigorous design methods that allow us to master the complexity and verify the correctness of our designs in a formal way. The formal RTM design can be verified earlier in the development process before implementation, which early verification can reduce the cost of fixing potential failures which can be very demanding in testing the system after implementation. In addition, the formal model of a RTM system can be automatically translated into executable code to be executed on the hardware. Automatic code generation reduces the efforts of hand-coded implementation and is portable across different architectures and Operating Systems (OSs). In this paper we propose a formal approach toward automatic generation of RTM system code, for a video decoder application, from a verified formal model of a RTM. The formal model of the RTM system is developed using the Event-B formal modelling language and is verified using theorem proving and model checking. The automatically generated RTM system has been integrated in an embedded platform as a Linux governor, and provides up to 4% improvement over Linux's default Ondemand governor.

关键词： Linux embedded systems formal verification power aware computing program compilers theorem proving Event-B formal modelling language Linux governor RTM system code automatic code generation formal methods model checking run-time power management video decoder Algorithm design and analysis Decoding Hardware Learning (artificial intelligence) Mathematical model Monitoring Prediction algorithms Embedded systems theorem proving power aware computing Transfer molding video decoder Algorithm design and analysis compilers Prediction algorithms Linux Model checking Formal verification Computer hardware DECODING Code generation Runtime

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Work-in-Progress: Porting new Versatile video Coding transforms to a heterogeneous GPU-based technology

Work-in-Progress: Porting new Versatile Video Coding transfo...

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Embedded Systems Week / Int Conf on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) / International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) / Int Conf on Embedded Software (EMSOFT)

作者： Floriano Vazquez, Manuel Saha, Anup Medina Morillas, Rafael Chavarrias Lapastora, Miguel Pescador del Oso, Fernando Univ Politecn Madrid CITSEM Madrid Spain

ISBN: (纸本)9781450369251

The sustained increase in the video digital features and traffic requirements across the networks is demanding more efficiency from both, video coding standards and platforms. In this context, a first version of the future de facto standard, Versatile video Coding (VVC), is partially migrated to a GPU-based architecture integrated into a heterogeneous platform. Results show an improvement of 11 times for the new Adaptive Multiple Transform (AMT) transforms.

关键词： GPU VVC HEVC AMT video decoder

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Many-Core Display Stream Compression decoders With Simplified Pixel Prediction 66

Many-Core Display Stream Compression Decoders With Simplifie...

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2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

作者： Wu, Shifu Baas, Bevan University of California Department of Electrical and Computer Engineering Davis United States

ISBN: (纸本)9798350302103

The video Electronics Standards Association (VESA) Display Stream Compression (DSC) video codec has been widely accepted to compress video streams over display links. This paper presents three many-core software DSC decoder implementations which utilize fine-grained task-level parallelism and are implemented with 65-265 processor cores and 2-6 memory modules. The designs achieve reduced complexity and increased energy efficiency by supporting modified medianadaptive prediction (MMAP) and midpoint prediction (MPP) to predict pixel values, but not the optional block prediction (BP), which causes minor degradation of rendered quality on only certain image types. The implementations achieve up to 24-96 1080p frames per second at 1.1 V and 1.75 GHz, and as low as 8.4 nJ per 4:2:0 pixel at 0.76 V and 678 MHz. Compared to the many-core DSC decoders that support BP, the proposed decoders occupy 1.32-1.33x smaller chip area, achieve 1.33-1.34x higher throughput per area and 1.25-1.29x lower energy per pixel. © 2023 IEEE.

关键词： block prediction (BP) Display Stream Compression (DSC) many-core video decoder

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"Magic Lantern" videodekodér pro fotoaparát Canon 5D

"Magic Lantern" videodekodér pro fotoaparát Canon 5D

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作者： Škvařilová, Radka Brno University of Technology

Tato práce představuje návrh na vytvoření dekodéru pro video zaznamenané pomocí softwaru Magic Lantern, který může být nainstalován na Canon 5D. Toto video je význačn&... 详细信息

Tato práce představuje návrh na vytvoření dekodéru pro video zaznamenané pomocí softwaru Magic Lantern, který může být nainstalován na Canon 5D. Toto video je význačné pro svoji velikost 14-bitů v raw formátu a proto může produkovat velmi kvalitní výstup. Práce má za cíl rozdělit video do jednotlivých snímků, ve vhodném formátu, který umí pracovat také s formáty obrazů s vysokým dynamickým rozsahem.

关键词： Magic Lantern Canon 5D vysoký dynamický rozsah video dekodér Magic Lantern Canon 5D High Dynamic Range video decoder Text

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A Bandwidth Optimized, 64 Cycles/NIB Joint Parameter decoder Architecture for Ultra High Definition H.264/AVC Applications

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2010年第8期E93A卷 1425-1433页

作者： Zhou, Jinjia Zhou, Dajiang He, Xun Goto, Satoshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840 x 2160@60 fps decoding at less than 133 MHz, with 37.2k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 4 x 4 block to DRAM.

关键词： motion vector derivation DRAM bandwidth ultra high resolution video decoder H.264/AVC

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A Parallelization Technique with Integrated Multi-Threading for video Decoding on Multi-core Systems

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KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS 2013年第10期7卷 2479-2496页

作者： Hong, Jung-Hyun Kim, Won-Jin Chung, Ki-Seok Hanyang Univ Dept Elect & Comp Engn Seoul 133791 South Korea SAMSUNG Elect DMC R&D Ctr Design Solut Lab Seoul South Korea Hanyang Univ Dept Elect Engn Seoul 133791 South Korea

Increasing demand for Full High-Definition (FHD) video and Ultra High-Definition (UHD) video services has led to active research on high speed video processing. Widespread deployment of multi-core systems has accelerated studies on high resolution video processing based on parallelization of multimedia software. Even if parallelization of a specific decoding step may improve decoding performance partially, such partial parallelization may not result in sufficient performance improvement. Particularly, entropy decoding has often been considered separately from other decoding steps since the entropy decoding step could not be parallelized easily. In this paper, we propose a parallelization technique called Integrated Multi-Threaded Parallelization (IMTP) which takes parallelization of the entropy decoding step, with other decoding steps, into consideration in an integrated fashion. We used the Simultaneous Multi-Threading (SMT) technique with appropriate thread scheduling techniques to achieve the best performance for the entire decoding step. The speedup of the proposed IMTP method is up to 3.35 times faster with respect to the entire decoding time over a conventional decoding technique for H.264/AVC videos.

关键词： H.264/AVC video decoder multi-core systems parallel processing

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High-performance spatial and temporal error-concealment algorithms for block-based video coding techniques

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ETRI JOURNAL 2005年第1期27卷 53-63页

作者： Hsu, CT Chen, MJ Liao, WW Lo, SY Natl Dong Hwa Univ Dept Elect Engn Hualien Taiwan

A compressed video bitstream is sensitive to errors that may severely degrade the reconstructed images even when the bit error rate is small. One approach to combat the impact of such errors is the use of error concealment at the decoder without increasing the bit rate or changing the encoder. For spatial-error concealment, we propose a method featuring edge continuity and texture preservation as well as low computation to reconstruct more visually acceptable images. Aiming at temporal error concealment, we propose a two-step algorithm based on block matching principles in which the assumption of smooth and uniform motion for some adjacent blocks is adopted. As simulation results show, the proposed spatial and temporal methods provide better reconstruction quality for damaged images than other methods.

关键词： error concealment video decoder H.263.

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Bringing Alive Blurred Moments

Bringing Alive Blurred Moments

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IEEE/CVF Conference on Computer Vision and Pattern Recognition

作者： Kuldeep Purohit Anshul Shah A. N. Rajagopalan Indian Institute of Technology Madras University of Maryland

ISBN: (纸本)9781728132945

We present a solution for the goal of extracting a video from a single motion blurred image to sequentially reconstruct the clear views of a scene as beheld by the camera during the time of exposure. We first learn motion representation from sharp videos in an unsupervised manner through training of a convolutional recurrent video au-toencoder network that performs a surrogate task of video reconstruction. Once trained, it is employed for guided training of a motion encoder for blurred images. This network extracts embedded motion information from the blurred image to generate a sharp video in conjunction with the trained recurrent video decoder. As an intermediate step, we also design an efficient architecture that enables real-time single image deblurring and outperforms competing methods across all factors: accuracy, speed, and compactness. Experiments on real scenes and standard datasets demonstrate the superiority of our framework over the state-of-the-art and its ability to generate a plausible sequence of temporally consistent sharp frames.

关键词： image blur videotapes BLURRING video decoder image reconstruction exposure time Cameras Training Moment of force

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360 DEGREES video CODING USING REGION ADAPTIVE SMOOTHING

360 DEGREES VIDEO CODING USING REGION ADAPTIVE SMOOTHING

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IEEE International Conference on Image Processing

作者： Madhukar Budagavi John Furton Guoxin Jin Ankur Saxena Jeffrey Wilkinson Andrew Dickerson Samsung Research America Northwestern University

ISBN: (纸本)9781479983407

360 degrees video is emerging as a new way of experiencing immersive video due to the ready availability of powerful handheld devices such as smartphones. 360 degrees video enables immersive "real life", "being there" experience for consumers by capturing the 360 degree view of the world. Users can change their viewpoint and dynamically view any part of the captured scene they desire. 360 degrees video requires higher bitrate than conventional video due to increased video resolution (4K and beyond) needed to support the wider field of view. Efficient compression of 360 degrees video is thus needed to provide high quality immersive video viewing experience to consumers. This paper provides an overview of 360 degrees video and presents a region adaptive video smoothing technique that exploits the unique characteristics of 360 degrees video to provide up to 20% bitrate savings with minimal perceptual quality degradation while requiring no modifications to the video decoder.

关键词： 360 degrees video video coding H.264/AVC HEVC/H.265 videotapes video coding COPPER ALLOY NO 360 field of view video decoder smoothing Consumers Bit rate

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REDUCING POWER CONSUMPTION OF HEVC CODEC WITH LOSSLESS REFERENCE FRAME RECOMPRESSION

REDUCING POWER CONSUMPTION OF HEVC CODEC WITH LOSSLESS REFER...

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IEEE International Conference on Image Processing

作者： Dajiang Zhou Li Guo Jinjia Zhou Satoshi Goto Graduate School of Information Production and Systems Waseda University

ISBN: (纸本)9781479957521

Motion estimation and motion compensation in HEVC and similar video codecs involve huge memory traffic in storing and loading reference frames. The resulting memory power composes a significant portion of system energy consumption. This paper presents a memory power reduction framework that losslessly compresses and decompresses reference frames on-the-fly. We first present the architecture that supports the random access of frame data compressed in variable ratios. The latest recompression algorithms and the corresponding VLSI implementation are also introduced. The framework has been implemented in several UHDTV ASIC and FPGA codecs. Experiments under HEVC common test conditions show an average memory traffic reduction of near 60%.

关键词： H.265 HEVC H.264 AVC Embedded compression Lossless Frame recompression video decoder video encoder Power consumption

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