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Enhanced Intra String Copy for Screen Content coding in AVS3

IEEE ACCESS 2022年 10卷 80403-80414页

作者： Zhao, Liping Wang, Huihui Zhou, Qingyang Zhang, Wenjuan Zhou, Kailun Hu, Keli Lin, Tao Shaoxing Univ Dept Comp Sci & Engn Shaoxing 312000 Peoples R China Peking Univ Informat Technol Res & Dev Innovat Ctr Shaoxing 312000 Peoples R China Tongji Univ Coll Elect & Informat Engn VLSI Lab Shanghai 200092 Peoples R China

Driven by growing applications that use computer screens as interfaces for daily remote interactions, almost all current video coding standards have included screen content coding (SCC) tools. Recently, an efficient SCC tool called intra string copy (ISC) has been adopted in the third-generation of audio video coding standard in China (AVS3). ISC has two coding unit (CU) level sub-modes: fully-matching-string and partially-matching-string based string prediction (FPSP) sub-mode and equal-value-string, unit-basis-vector-string, and unmatched-pixel-string based string prediction (EUSP) sub-mode. To further improve the coding efficiency of SCC, this paper proposes four enhancement techniques of ISC (EISC), including CU partition improvements, point vector (PV) relocation and reactivation, line-based overlapping string prediction, and an optimized coding method for string length in the EUSP sub-mode. Compared with the latest AVS3 reference software HPM with EISC disabled, using AVS3 SCC common test condition and YUV test sequences in text and graphics with motion and mixed content categories, the proposed technique achieves an average Y BD-rate reduction of 2.39% and 1.49% for all intra (AI) and low-delay B (LDB) configurations, respectively, with low additional encoding complexity and almost no additional decoding complexity. All proposed ISC enhancement techniques have been adopted in AVS3.

关键词： Encoding Complexity theory Copper standards Frequency modulation Hardware Transforms video coding standard screen content coding intra string copy string split point vector

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Fast prediction mode selection and CU partition for HEVC intra coding

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IET IMAGE PROCESSING 2020年第9期14卷 1892-1900页

作者： Fu, Bin Zhang, Qiangqing Hu, Jianling Soochow Univ Sch Elect & Informat Engn Suzhou 215006 Jiangsu Peoples R China

Compared with the predecessor H.264/advanced video coding, high-efficiency video coding (HEVC) is a new video coding standard with nearly double coding efficiency under the same coding quality. However, the computing complexity of HEVC increases sharply. To solve this problem, a fast algorithm for intra prediction mode selection based on mode grouping is proposed by reducing the number of modes entering rough mode decision. Moreover, the dual support vector machine is proposed to efficiently select the coding unit (CU) size, which is based on texture features of CU and sub-CUs including content complexity and direction complexity. By using the new CU size selection algorithm, the encoder can confirm the split for complex CU and terminate the split for simple CU in advance, so as to reduce the computing complexity of CU size selection. The experimental results show that by employing the two fast algorithms in intra coding, it can save 42.80% encoding time, with 0.98% increment in bit rate and 0.018 dB loss of peak-signal-to-noise ratio of luminance, compared with the reference software x265-1.7.

关键词： computational complexity support vector machines video coding rate distortion theory complex CU CU size selection algorithm direction complexity coding unit size dual support vector machine rough mode decision mode grouping intra prediction mode selection computing complexity coding quality double coding efficiency video coding standard high-efficiency video coding HEVC intra coding CU partition fast prediction mode selection

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High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter

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IET CIRCUITS DEVICES & SYSTEMS 2015年第5期9卷 377-383页

作者： Srinivasarao, Batta Kota Naga Chakrabarti, Indrajit Ahmad, Mohammad Nawaz Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual-standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 x 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 x 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 x 4320) frame in HEVC standard.

关键词： video coding image filtering mathematics computing VLSI field programmable gate arrays high-speed low-power very-large-scale integration architecture video coding standard multimedia application HEVC high efficiency video coding video resolution H 264-AVC standard decoder dual-standard deblocking filter architecture Matlab simulation VLSI architecture FPGA ASIC domain 4K ultra high definition 8K UHD 4K UHD power 5 80 mW frequency 100 MHz time 8 42 ms time 18 ms

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Efficient frame-level bit allocation algorithm for H.265/HEVC

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IET IMAGE PROCESSING 2017年第4期11卷 245-257页

作者： He, Jing Yang, Fuzheng Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China

Rate control (RC) plays a critical role in video coding for regulating the coded bit-stream to achieve the target bitrate, which involves two basic steps: bit allocation (BA) and quantisation parameter selection. Here, the former is a key element to directly affect the performance of RC. So, in this study, an efficient frame-level BA algorithm is proposed for the latest video coding standard H.265/high-efficiency video coding (HEVC). First, by analysing the optimisation problem of the frame-level BA, two factors have been found to be related to the frame-level BA, which are inter-frame dependency and the target bitrate. Then, a measure of inter-frame dependency is put forward to reflect the correlation among consecutive frames. Finally, according to the results of allocation weights through the dynamic programming method, the relationships among the allocation weights and the two factors are investigated, and based on which the efficient BA model is established. Experimental results show that in comparison with the original RC scheme in HM-14.0, the proposed frame-level BA algorithm reduces, on average, BD-rate by 5.19% with negligible encoding time increase. In addition, the proposed algorithm also achieves higher GOP-level RC accuracy compared with the original RC scheme in HM.

关键词： video coding optimisation H 265-high-efficiency video coding frame-level bit allocation rate control coded bit-stream target bit rate quantisation parameter selection video coding standard optimisation problem inter-frame dependency intra-frame complexity inter-frame complexity consecutive frames allocation weights dynamic programming BjOntegaard-delta rate group-of-picture-level RC accuracy

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Optimised HEVC encoder intra-only configuration

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IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第6期14卷 256-262页

作者： Bahri, Nejmeddine Khemiri, Randa Univ Sfax Lab Elect & Informat Technol Natl Sch Engn Sfax Sfax Tunisia Univ Monastir Lab Elect & Microelect Fac Sci Monastir Monastir Tunisia

High-efficiency video coding (HEVC) is the latest video coding standard aimed to reduce the bitrate by half for the same video quality compared to H.264/AVC. This encoding performance makes HEVC more suitable for high-definition video applications. However, this performance is coupled with a high-computational complexity, which makes it hard to achieve real-time video encoding with a classic embedded processor. Multicore technology of programmable processors could be a very promising solution to overcome this computational complexity. Moreover, software optimisations by proposing fast algorithms for the most complex functions could also be an efficient solution to speed up the encoding process. In this context, this study presents a fast mode decision algorithm for the intra prediction module. This algorithm aims to reduce the number of intra prediction modes to be tested instead of performing a full intra mode search. Experimental results for all-Intra configuration show that the proposed fast intra mode decision allows saving up to 46.79% of the intra prediction time in average. Encoding performance in terms of video quality and bitrate is not significantly affected.

关键词： optimisation high definition video computational complexity data compression video coding high-efficiency video coding video coding standard video quality high-definition video applications high-computational complexity real-time video encoding embedded processor multicore technology software optimisations intra prediction modes HEVC encoder intra-only configuration optimization

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The IEEE 1857 standard: Empowering Smart video Surveillance Systems

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IEEE INTELLIGENT SYSTEMS 2014年第5期29卷 30-39页

作者： Gao, Wen Tian, Yonghong Huang, Tiejun Ma, Siwei Zhang, Xianguo Peking Univ Sch Elect Engn & Comp Sci Beijing Peoples R China

The IEEE 1857 standard for Advanced Audio and video coding was released as IEEE 1857-2013 in June 2013. Despite consisting of several different groups, the most significant feature of IEEE 1857-2013 is its Surveillance Groups, which can not only achieve at least twice the coding efficiency on surveillance videos as H.264/AVC High Profile, but it"s the most analysis-friendly video coding standard. This article presents an overview of IEEE 1857 Surveillance Groups, highlighting background model-based coding technology and analysis-friendly functionalities. IEEE 1857-2013 will present new opportunities and drive research in smart video surveillance communities and industries.

关键词： IEEE standards audio coding video coding video surveillance H.264-AVC IEEE 1857 standard audio coding background model-based coding technology smart video surveillance video coding Audio coding Encoding Feature extraction IEEE 1857 standards video coding video surveillance IEEE 1857 background modeling intelligent systems surveillance video processing video coding standard

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A general method for detecting all-zero blocks prior to DCT and quantization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR video TECHNOLOGY 2007年第2期17卷 237-241页

作者： Xie, Zhengguang Liu, Yong Liu, James Yang, Tiejun Beijing Univ Posts & Telecommun Beijing 100876 Peoples R China Huihua Univ Huihua City 418008 Hunan Province Peoples R China W&W Commun Inc Santa Clara CA 95054 USA

This paper presents an innovative algorithm for detecting all-zero discrete cosine transform (DCT) coefficient blocks prior to DCT and quantization for all block-based video coding standards. A mathematic model is established based on analyzing DCT coefficient distribution and applying Paseval energy conservation theorem. The algorithm is applied to H.264 video coding and experimental results show up to 32% higher detection ratio without degrading video quality, compared with results of the existing methods. Furthermore, up to 47% higher detection ratio is achieved by changing the threshold based on DCT coefficient distribution. For motion estimation, much less search points needed by using the proposed method as early termination criterion than that by using the existing methods.

关键词： all-zero discrete cosine transform (DCT) coefficient blocks DCT coefficient distribution energy conservation theorem video coding standard

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Optimized Packetization of H.264 SVC Bitstreams for MIMO Wireless video Streaming 18

Optimized Packetization of H.264 SVC Bitstreams for MIMO Wir...

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18th International Symposium on Communications and Information Technologies (ISCIT)

作者： Tiawongsuwan, Manthana Tashiro, Koji Kurosaki, Masayuki Ochi, Hiroshi Kyushu Inst Technol Grad Sch Comp Sci & Syst Engn 680-4 Kawazu Iizuka Fukuoka Japan

ISBN: (纸本)9781538684580

Wireless video transmission over multiple-input multiple-output (MIMO) systems is a challenging theme. Eigen beam-space division multiplexing (E-SDM) is an optimal beamforming technique in terms of channel capacity when the transmitter and receiver can share channel state information. E-SDM sorts the channel quality from the highest signal-to-noise ratio (SNR) to the lowest one. This paper presents the video transmission scheme for H.264 scalable video streams over MIMO E-SDM with optimized packetization. The proposed method controls the ratio of a base layer and enhancement layers contained in a packet. The result shows that the optimized ratio is obtained when a packet consists of the lowest base layer ratio. This ratio provides the 39.9 dB of peak-signal-to-noise ratio after decoding while no frame can be decoded with the other ratio at SNR of 10 dB.

关键词： H.264 SVC MIMO E-SDM video streaming eigen beamforming video coding standard

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Decompressed video Enhancement via Accurate Regression Prior

Decompressed Video Enhancement via Accurate Regression Prior

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30th IEEE Conference on Visual Communications and Image Processing (VCIP)

作者： Shen, Tao Zhang, Yulun Zhang, Yongbing Wang, Xingzheng Wang, Haoqian Dai, Qionghai Tsinghua Univ Grad Sch Shenzhen Shenzhen 518055 Peoples R China Tsinghua Univ Dept Automat Beijing 100084 Peoples R China

ISBN: (纸本)9781509053162

There is an increasing need for high-quality multimedia applications based on block-based hybrid video coding. Inevitably, the frame will degrade during the process of block wise intra/inter prediction, transformation, and quantization, especially when the bit rate is low. In this paper, we propose an efficient decompressed video enhancement algorithm based on the adjusted anchored neighborhood regression (A+) method. In our work, first, we learn offline linear regressors, i.e. projection matrices from the decompressed to original video frames in the training phase. For grouping anchored neighborhoods more accurately, we adopt MI-KSVD rather than KSVD to learn the dictionary. Moreover, we exploit the mutual coherence between dictionary atoms and training samples to find the nearest neighbors. Second, in the enhancement phase, we boost the quality of input decompressed videos offline by learned regression priors. To verify the robustness of our enhancement method, extensive experiments are conducted. As shown in our experimental results, the proposed enhancement method yields superior performance both objectively and subjectively.

关键词： Dictionary learning image enhancement ridge regression video coding standard video decompression

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Hardware Accelerator for Dual standard Deblocking Filter 34

Hardware Accelerator for Dual Standard Deblocking Filter

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34th International Conference on VLSI Design / 20th International Conference on Embedded Systems (VLSID)

作者： Saravanan, P. Priyadarshini, B. Syndia Kanna, P. Vignesh Vaishnavi, P. PSG Coll Technol Dept ECE Coimbatore Tamil Nadu India

ISBN: (纸本)9781665440875

Advanced video coding (AVC) also known as H.264 is a popular video coding standard which is used in many image processing applications. In order to fulfill the increasing demand for better video quality with less complex designs, High Efficiency video coding (HEVC) also known as H.265 came into picture. HEVC provides better quality with half the bit rate required for processing in comparison with AVC. In case of AVC, the design of deblocking filter is more complex due to the filtering decisions, whereas HEVC is less complex and also supports parallel processing. As there is a need for high throughput and less complex deblocking filter, a novel dual standard deblocking filter is proposed in this work which supports both AVC and HEVC. In particular, a novel filtering order which enables four edges to be processed simultaneously has been proposed for both AVC and HEVC. For AVC, the proposed design takes 18 clock cycles to process a 16 x 16 macroblock and for HEVC standard, the proposed design takes 12 clock cycles to process a 16 x 16 coding transform unit (CTU). In addition to this, the proposed design supports parallel processing concept in HEVC. The proposed design is synthesized using Xilinx ISE 14.7 and is mapped to xc5vlx30-1ff324 Virtex-5 Field programmable gate array (FPGA). Thus it helps in increasing the execution speed of the design and it is also noted that there is a reduction in number of clock cycles needed for processing when compared with the existing architectures. The physical implementation of the proposed architecture is also carried out using Semiconductor Lab (SCL) 180 nm process node.

关键词： HEVC AVC Dual standard Deblocking filter Filtering order video coding standard

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