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Unified energy-efficient reconfigurable MAC for dynamic Convolutional Neural Network based on winograd algorithm

MICROPROCESSORS AND MICROSYSTEMS 2022年 93卷

作者： Yang, Dong-Sheng Xu, Chong-Hao Ruan, Shanq-Jang Huang, Chun-Ming Natl Taiwan Univ Sci & technol Comp Engn Coll Elect Engn & Comp Sci Dept Elect Taipei Taiwan Natl Appl Res Labs Taiwan Semicond Res Inst Taipei Taiwan

There has been a dramatic proliferation of research concerned with Convolutional Neural Networks (CNNs) over the past decade. In the field of smart surveillance, multi-channel frames need to be processed simultaneously as real-time operations, which leads to intensive computation. Deep CNNs have tens of layers which lead to intensive computation. In order to solve tremendous computation pressure, lots of CNN accelerators have been proposed. Moreover, many works focus on the design of a multiply-and-accumulate (MAC) unit since ten billions of MAC computations induce enormous energy consumption for logical operations in CNNs. Although DynCNN (Tsai et al., 2020) improves the structure of conventional CNNs by using the high similarity property of consecutive frames, it generates redundant cells and leads to redundant operations. Therefore, this paper proposed an energy-efficient reconfigurable MAC and a high-performance CNN accelerator based on the winograd Minimum Filtering algorithm (WMFA). The proposed design not only dramatically enhances throughput but also acquires better energy efficiency in limited resources. Experimental results showed that the proposed winograd processing element (PE) gives 8% to 12% power improvements. The DSP efficiency was improved in the range of from 1.48x to 6.82x as well compared with the previous works.

关键词： Convolutional Neural Networks (CNNs) CNN accelerators Processing element (PE) Dynamic convolution winograd algorithm

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Work-in-Progress: WinoNN: Optimising FPGA-based Neural Network Accelerators using Fast winograd algorithm

Work-in-Progress: WinoNN: Optimising FPGA-based Neural Netwo...

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ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Wang, Xuan Wang, Chao Zhou, Xuehai Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (纸本)9781538655627

In this paper, we present WinoNN, which utilizes fast winograd algorithm to optimize FPGA-based neural network accelerators. In particular, winograd algorithm effectively reduces the resource occupation of FPGA, as well as boosts the system speedup, especially for embedded and mobile devices. The main contributions of this paper include implementation of single-channel convolution module, implementation of multi-channel convolution module, deployment and performance test on FPGA hardware platform. We use LeNet-5 as a case study, which demonstrates the performance of WinoNN is significantly better than the general ARM Cortex A series processors.

关键词： winograd algorithm FPGA Accelerator

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winograd algorithm for 3D Convolution Neural Networks 26th

Winograd Algorithm for 3D Convolution Neural Networks

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26th International Conference on Artificial Neural Networks (ICANN)

作者： Wang, Zelong Lan, Qiang He, Hongjun Zhang, Chunyuan Natl Univ Def Technol Dept Comp Sci Changsha 410003 Hunan Peoples R China

ISBN: (纸本)9783319686127;9783319686110

Three-dimensional convolution neural networks (3D CNN) have achieved great success in many computer vision applications, such as video analysis, medical image classification, and human action recognition. However, the efficiency of this model suffers from great computational intensity. In this work, we reduce the algorithmic complexity of 3D CNN to accelerate this model with winograd's minimal algorithm. We benchmark a net model on GPU platform, resulting in a speed-up by a factor of 1.2x compared with cuDNN, which is commonly used in many current machine learning frameworks.

关键词： winograd algorithm 3D CNN algorithmic complexity

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WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress) 18

WinoNN: optimising FPGA-based neural network accelerators us...

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Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis

作者： Xuan Wang Chao Wang Xuehai Zhou University of Science and Technology of China Hefei China

ISBN: (纸本)9781538655627

In this paper, we present WinoNN, which utilizes fast winograd algorithm to optimize FPGA-based neural network accelerators. In particular, winograd algorithm effectively reduces the resource occupation of FPGA, as well as boosts the system speedup, especially for embedded and mobile devices. The main contributions of this paper include implementation of single-channel convolution module, implementation of multichannel convolution module, deployment and performance test on FPGA hardware platform. We use LeNet-5 as a case study, which demonstrates the performance of WinoNN is significantly better than the general ARM Cortex A series processors.

关键词： accelerator winograd algorithm FPGA

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WRA-SS: A High-Performance Accelerator Integrating winograd With Structured Sparsity for Convolutional Neural Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第1期32卷 164-177页

作者： Yang, Chen Meng, Yishuo Xi, Jiawei Xiang, Siwei Wang, Jianfei Mei, Kuizhi Xi An Jiao Tong Univ Sch Microelect Xian 710049 Shaanxi Peoples R China

Sparsification for convolutional neural networks (CNNs) and convolution acceleration algorithms such as the winograd algorithm are two efficient ways to reduce the intensive computations of existing CNNs. To better combine the sparsification and winograd algorithm, a close integration method is proposed to dynamically reduce the invalid parameters following the winograd transformation. To address the limitation of data bandwidth, a hierarchical two-level storage structure and corresponding data scheduling scheme are proposed, which can realize a conflict-free scheduling process. In addition, an algorithm hardware codesign method is proposed to efficiently and flexibly reduce the invalid computations led by the previous filter decomposition method. The accelerator is evaluated on Xilinx XCVU9P FPGA, reaching 412-MHz clock frequency. Compared to state-of-the-art designs, WRA-SS can achieve 1.54-5.33x and 1.17-7.39x performance improvement for VGG-16 under 80% weight sparsity and 0% weight sparsity, respectively.

关键词： Convolutional neural network data storage and schedule sparse neural network winograd algorithm

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Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D winograd Units

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第3期43卷 919-932页

作者： Yang, Chen Yang, Yaoyao Meng, Yishuo Huo, Kaibo Xiang, Siwei Wang, Jianfei Geng, Li Xi An Jiao Tong Univ Sch Microelect Xian 710049 Shaanxi Peoples R China

General convolution acceleration, such as winograd and FFT, is a promising direction to address the computational complexity of current convolutional neural networks (CNNs). However, the flexibility of these CNNs makes this kind of scheme always introduce massive redundant computations, damaging the acceleration effect. In this article, a two-stage splitting method for arbitrarily sized tensors and filters and a unified hardware architecture using layer-adaptive allocated winograd units are proposed, achieving effective redundance elimination and unified architecture. First, a tensor adaptive presplitting method is proposed to divide the original tensors to match the rule of winograd. Furthermore, a winograd-based extended splitting scheme is designed to reduce the redundant calculations;therefore, a substantial reduction in multiplication operations in convolutional layers achieved 30.6%-75% savings. Finally, a unified hardware architecture with a layer-adaptive allocation method is proposed to evaluate and select the optimal winograd F(m, r) units and input/output parallelisms. This architecture is evaluated based on the Xilinx XCVU9P platform and achieves 1.97/1.23/1.60/1.25 GOPS/DSP for AlexNet, VGG16, modified VGG16, and ResNet18, respectively. It achieves up to 5.81x improvements in DSP efficiency compared with previous FPGAbased designs.

关键词： Filtering algorithms Convolution Tensors Hardware Computer architecture Parallel processing Optimization Convolutional neural network (CNN) acceleratio two-stage splitting unified hardware generation winograd algorithm

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APW: Asymmetric Padded winograd to Reduce Thread Divergence for Computational Efficiency on SIMT Architecture

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2025年第5期E108D卷 436-439页

作者： Lee, Wonho Kwak, Jong Wook Yeungnam Univ Yeungnam South Korea

In this letter, we propose Asymmetric Padded winograd called APW, designed to enhance the computational efficiency of winograd-based convolution algorithms on SIMT architectures. This approach resolves thread divergence, which typically causes delays in execution due to uneven computational distribution across threads. By integrating asymmetric padding into both filters and inputs, APW unifies the size of sub-filters and sub-inputs. This uniformity maintains a consistent execution path for threads throughout winograd-based convolution process, effectively minimizing thread divergence. Our experimental results demonstrate that APW substantially reduces thread divergence observed in previous work to nearly zero and cuts down the total execution time by up to 17.78%.

关键词： asymmetric padding thread divergence winograd algorithm convolution acceleration SIMT architecture

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Efficient Super-Resolution System With Block-Wise Hybridization and Quantized winograd on FPGA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第11期42卷 3910-3924页

作者： Shi, Bizhao Zhang, Jiaxi He, Zhuolun Wei, Xuechao Li, Sicheng Luo, Guojie Zheng, Hongzhong Xie, Yuan Peking Univ Sch Comp Sci Beijing 100871 Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Peoples R China Alibaba DAMO Acad Beijing 100102 Peoples R China Peking Univ Ctr Energy Efficient Comp & Applicat Beijing 100871 Peoples R China Alibaba DAMO Acad Sunnyvale CA 94085 USA

Super-resolution (SR) techniques aim to restore a high-resolution (HR) image from low-resolution (LR) images, which are often used to assist the enhancement of image/video quality under the rapid development of HR and high-frame-rate media. Recently, neural network (NN)-based methods perform much better image reconstruction quality than classical approaches. However, the unacceptable computation complexity as well as the huge memory footprints of NNs limit the throughputs and scalability of these SR systems. In this work, we analyze several key issues in the design of NN-based SR systems first. Then, we propose a three-level systematic optimization methodology for SR systems to reduce computation overhead and keep image quality. At the algorithm level, we introduce image blocking to SR tasks and develop a block-wise SR algorithm based on the hybrid of NN and interpolation with a consistent image block evaluation metric. The configurable hybrid parameters help the SR algorithm to achieve a flexible tradeoff between the computation overhead and image quality. At the operator level, we focus on the transpose convolution operators commonly used for upsampling in SR NNs. We propose an efficient winograd-based transposed convolution acceleration method. Through the efficient subconvolutions conversion and the winograd specialization, this methods enables unified winograd transformations and simplified data access patterns. At the data level, we propose a novel quantization method for winograd-aware SR NNs to get better-quantized accuracy. Comprehensive evaluations demonstrate the effectiveness of these optimizations. Our SR system reduces a large number of multiplications with great scalability and supports 4K@120 fps and 8K@30 fps outputs with acceptable image quality degradation.

关键词： Convolution Optimization Interpolation Image quality Streaming media Scalability Costs FPGA accelerator quantization super-resolution (SR) transposed convolution (TCONV) winograd algorithm

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An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2022年第11期30卷 1587-1600页

作者： Li, Shengzhao Wang, Qin Jiang, Jianfei Sheng, Weiguang Jing, Naifeng Mao, Zhigang Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Dept Micro Nano Elect Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ Natl Key Lab Sci & Technol Micro Nano Fabricat Shanghai 200240 Peoples R China

Convolutional neural networks (CNNs) have had great success when applied to computer vision technology, and many application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) CNN accelerators have been proposed. These accelerators primarily focus on the acceleration of a single input, and they are not particularly optimized for video applications. In this article, we focus on the similarities between continuous inputs in video, and we propose a YOLOv3-tiny CNN FPGA accelerator using incremental operation. The accelerator can skip the convolution operation of similar data between continuous inputs. We also use the winograd algorithm to optimize the conv3 x 3 operator in the YOLOv3-tiny network to further improve the accelerator's efficiency. Experimental results show that our accelerator achieved 74.2 frames/s on ImageNet ILSVRC2015. Compared to the original network without winograd algorithm and incremental operation, our design provides a 4.1 x speedup. When compared with other YOLO network FPGA accelerators applied to video applications, our design provided a 3.13 x -18.34x normalized digital signal processor (DSP) efficiency and 1.10 x -14.2x energy efficiency.

关键词： Convolutional neural network (CNN) field-programmable gate array (FPGA) accelerator incremental operation input similarity video applications winograd algorithm

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FPGA-Oriented Target Detection Accelerator Design 5

FPGA-Oriented Target Detection Accelerator Design

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5th International Conference on Frontiers Technology of Information and Computer, ICFTIC 2023

作者： Huang, Weizhe Harbin University of Science and Technology School of Measurement and Control Technology and Communication Engineering Harbin China

ISBN: (纸本)9798350309034

Target detection is widely applied in fields such as face recognition, autonomous driving, and industrial automation. However, when deploying target detection models based on convolutional neural networks on resource-constrained embedded platforms, issues like high computational complexity, long execution times, and significant on-chip memory usage arise. To address these challenges, this paper presents a target detection accelerator design based on Field Programmable Gate Array (FPGA). Firstly, the computational workload of convolutional neural networks is reduced by merging convolutional layers with batch normalization layers. Secondly, to mitigate on-chip storage space concerns, on-chip data fixed-point quantization is employed to decrease on-chip memory consumption. Subsequently, to tackle the issue of long execution times, a convolution calculation module based on the winograd algorithm is designed, which reduces computation latency. Finally, a dual-buffer pipeline architecture is devised to optimize memory bandwidth. Experimental results demonstrate that the proposed solution accelerates YOLOv4-tiny on the ZYNQ-7020, achieving a performance of 21.35 GOP/s. The energy efficiency is 32.56 times higher than CPU and 9.76 times higher than GPU. Additionally, the convolution calculation module in this paper reduces inference time by 15% compared to the sliding window convolution calculation method. © 2023 IEEE.

关键词： CNN FPGA target detection winograd algorithm

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