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26th International Conference on Artificial Neural Networks (ICANN)

作者： Wang, Zelong Lan, Qiang He, Hongjun Zhang, Chunyuan Natl Univ Def Technol Dept Comp Sci Changsha 410003 Hunan Peoples R China

ISBN: (纸本)9783319686127;9783319686110

Three-dimensional convolution neural networks (3D CNN) have achieved great success in many computer vision applications, such as video analysis, medical image classification, and human action recognition. However, the efficiency of this model suffers from great computational intensity. In this work, we reduce the algorithmic complexity of 3D CNN to accelerate this model with winograd's minimal algorithm. We benchmark a net model on GPU platform, resulting in a speed-up by a factor of 1.2x compared with cuDNN, which is commonly used in many current machine learning frameworks.

关键词： winograd algorithm 3D CNN algorithmic complexity

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Work-in-Progress: WinoNN: Optimising FPGA-based Neural Network Accelerators using Fast winograd algorithm

Work-in-Progress: WinoNN: Optimising FPGA-based Neural Netwo...

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ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Wang, Xuan Wang, Chao Zhou, Xuehai Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China

ISBN: (纸本)9781538655627

In this paper, we present WinoNN, which utilizes fast winograd algorithm to optimize FPGA-based neural network accelerators. In particular, winograd algorithm effectively reduces the resource occupation of FPGA, as well as boosts the system speedup, especially for embedded and mobile devices. The main contributions of this paper include implementation of single-channel convolution module, implementation of multi-channel convolution module, deployment and performance test on FPGA hardware platform. We use LeNet-5 as a case study, which demonstrates the performance of WinoNN is significantly better than the general ARM Cortex A series processors.

关键词： winograd algorithm FPGA Accelerator

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Unified energy-efficient reconfigurable MAC for dynamic Convolutional Neural Network based on winograd algorithm

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MICROPROCESSORS AND MICROSYSTEMS 2022年 93卷

作者： Yang, Dong-Sheng Xu, Chong-Hao Ruan, Shanq-Jang Huang, Chun-Ming Natl Taiwan Univ Sci & technol Comp Engn Coll Elect Engn & Comp Sci Dept Elect Taipei Taiwan Natl Appl Res Labs Taiwan Semicond Res Inst Taipei Taiwan

There has been a dramatic proliferation of research concerned with Convolutional Neural Networks (CNNs) over the past decade. In the field of smart surveillance, multi-channel frames need to be processed simultaneously as real-time operations, which leads to intensive computation. Deep CNNs have tens of layers which lead to intensive computation. In order to solve tremendous computation pressure, lots of CNN accelerators have been proposed. Moreover, many works focus on the design of a multiply-and-accumulate (MAC) unit since ten billions of MAC computations induce enormous energy consumption for logical operations in CNNs. Although DynCNN (Tsai et al., 2020) improves the structure of conventional CNNs by using the high similarity property of consecutive frames, it generates redundant cells and leads to redundant operations. Therefore, this paper proposed an energy-efficient reconfigurable MAC and a high-performance CNN accelerator based on the winograd Minimum Filtering algorithm (WMFA). The proposed design not only dramatically enhances throughput but also acquires better energy efficiency in limited resources. Experimental results showed that the proposed winograd processing element (PE) gives 8% to 12% power improvements. The DSP efficiency was improved in the range of from 1.48x to 6.82x as well compared with the previous works.

关键词： Convolutional Neural Networks (CNNs) CNN accelerators Processing element (PE) Dynamic convolution winograd algorithm

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WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress) 18

WinoNN: optimising FPGA-based neural network accelerators us...

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Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis

作者： Xuan Wang Chao Wang Xuehai Zhou University of Science and Technology of China Hefei China

ISBN: (纸本)9781538655627

In this paper, we present WinoNN, which utilizes fast winograd algorithm to optimize FPGA-based neural network accelerators. In particular, winograd algorithm effectively reduces the resource occupation of FPGA, as well as boosts the system speedup, especially for embedded and mobile devices. The main contributions of this paper include implementation of single-channel convolution module, implementation of multichannel convolution module, deployment and performance test on FPGA hardware platform. We use LeNet-5 as a case study, which demonstrates the performance of WinoNN is significantly better than the general ARM Cortex A series processors.

关键词： accelerator winograd algorithm FPGA

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APW: Asymmetric Padded winograd to Reduce Thread Divergence for Computational Efficiency on SIMT Architecture

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IEICE Transactions on Information and Systems 2025年第5期E108.D卷 436-439页

作者： Lee, Wonho Kwak, Jong Wook Yeungnam University Korea Republic of

In this letter, we propose Asymmetric Padded winograd called APW, designed to enhance the computational efficiency of winograd-based convolution algorithms on SIMT architectures. This approach resolves thread divergence, which typically causes delays in execution due to uneven computational distribution across threads. By integrating asymmetric padding into both filters and inputs, APW unifies the size of sub-filters and sub-inputs. This uniformity maintains a consistent execution path for threads throughout winograd-based convolution process, effectively minimizing thread divergence. Our experimental results demonstrate that APW substantially reduces thread divergence observed in previous work to nearly zero and cuts down the total execution time by up to 17.78%. Copyright © 2025 The Institute of Electronics, Information and Communication Engineers.

关键词： asymmetric padding convolution acceleration SIMT architecture thread divergence winograd algorithm

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VLSI ARCHITECTURE FOR THE winograd FOURIER-TRANSFORM algorithm

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING AND MICROPROGRAMMING 1994年第9期40卷 605-616页

作者： GOPAL, B MANOHAR, S INDIAN INST SCI DEPT COMP SCI & AUTOMATBANGALORE 560012KARNATAKAINDIA INDIAN INST SCI CTR SUPERCOMP EDUC & RESBANGALORE 560012KARNATAKAINDIA

A simple systolic architecture for the computation of the DFT using the winograd Fourier Transform algorithm is presented. The architecture is shown to be problem-size independent and to satisfy the limited bandwidth constraint. By satisfying the above constraints, it is then shown to be naturally scalable within the limits allowed by the winograd algorithm. The proposed architecture is compared with existing VLSI solutions using winograd's technique. Lastly, the feasibility of deriving and using winograd type algorithms for larger primes and prime-powers is studied.

关键词： DISCRETE FOURIER TRANSFORM SPECIAL-PURPOSE VLSI ARCHITECTURE winograd algorithm SYSTOLIC ARCHITECTURE

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Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第7期39卷 1442-1455页

作者： Shen, Junzhong Huang, You Wen, Mei Zhang, Chunyuan Natl Univ Def Technol Coll Comp Changsha 410073 Peoples R China

3-D convolutional neural networks (3-D CNNs) are used efficiently in many computer vision applications. Most previous work in this area has concentrated only on design and optimization of accelerators for 2-D CNNs, with few attempts having been made to accelerate 3-D CNNs on FPGA. We find the acceleration of 3-D CNNs on FPGA to be challenging due to their high computational complexity and storage demands. More importantly, although the computational patterns of 2-D and 3-D CNNs are analogous, the conventional approaches that have been adopted for acceleration of 2-D CNNs may be unfit for 3-D CNN acceleration. In this paper, in order to accelerate 2-D and 3-D CNNs using a uniform framework, we first propose a uniform template-based architecture that uses templates based on the winograd algorithm to ensure the rapid development of 2-D and 3-D CNN accelerators. Then, with the aim of efficiently mapping all layers of 2-D/3-D CNNs onto a pipelined accelerator, techniques are developed to improve the throughput and computational efficiency of the accelerator, including layer fusion, layer clustering, and workload-balancing scheme. Finally, we demonstrate the effectiveness of the deep pipelined architecture by accelerating real-life 2-D and 3-D CNNs on the state-of-the-art FPGA platform. On VCU118, we achieve 3.7 TOPS for VGG-16, which outperforms state-of-the-art FPGA-based CNN accelerators. Comparisons with CPU and GPU solutions demonstrate that our implementation of 3-D CNN achieves gains of up to 17.8x and 64.2x in performance and energy relative to a CPU solution, and a 5.0x energy efficiency gain over a GPU solution.

关键词： Three-dimensional displays Two dimensional displays Field programmable gate arrays Acceleration Computer architecture Convolution Space exploration 3-D convolutional neural networks (3-D CNNs) uniform templates winograd algorithm

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A tile-fusion method for accelerating winograd convolutions

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NEUROCOMPUTING 2021年 460卷 9-19页

作者： Ji, Zeyu Zhang, Xingjun Wei, Zheng Li, Jingbo Wei, Jia Xi An Jiao Tong Univ Sch Comp Sci & Technol Xian 710049 Peoples R China

Compared with fast convolution methods such as im2col and the fast Fourier transform, winograd-based convolution, which has been widely applied to accelerate convolutional neural networks (CNNs), can provide high performance with smaller filters. Although there are several reported studies on the algorithmic optimization of CNNs, most of them are targeted at hardware architectures. The existing implementations of the winograd method perform well below what one would expect, due to the fact that the tile size of winograd-based convolution is usually empirical and the features of each convolution layer are ignored. This study aims to fill this gap and focuses on the efficient implementation of winograd based convolution in the CNN model. Specifically, we discuss the causes of poor performance, calculate the coefficient of computation complexity model and demonstrate a speedup in the inference process using an elaborate tile-fusion method, which derives the optimal tile size for each convolution layer in a CNN model. Compared with the representative existing implementations of CuDNN with a 4 x 4 tile, Arm Compute Library with a 6 x 6 tile, and NNPACK with an 8 x 8 tile, the results show significant performance improvements on of up to 1.89 x , 1.29 x and 1.17 x , respectively. (c) 2021 Published by Elsevier B.V.

关键词： Fast convolution winograd algorithm Parallel algorithm Convolutional neural network Tile size Zero padding

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Error Analysis and Improving the Accuracy of winograd Convolution for Deep Neural Networks

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ACM TRANSACTIONS ON MATHEMATICAL SOFTWARE 2020年第4期46卷 37-37页

作者： Barabasz, Barbara Anderson, Andrew Soodhalter, Kirk M. Gregg, David Trinity Coll Dublin Sch Comp & Stat Dublin 2 Ireland Trinity Coll Dublin Sch Math Dublin 2 Ireland

Popular deep neural networks (DNNs) spend the majority of their execution time computing convolutions. The winograd family of algorithms can greatly reduce the number of arithmetic operations required and is used in many DNN software frameworks. However, the performance gain is at the expense of a reduction in floating point (FP) numerical accuracy. In this article, we analyse the worst-case FP error and derive an estimation of the norm and conditioning of the algorithm. We show that the bound grows exponentially with the size of the convolution. Further, the error bound of the modified algorithm is slightly lower but still exponential. We propose several methods for reducing FP error. We propose a canonical evaluation ordering based on Huffman coding that reduces summation error. We study the selection of sampling "points" experimentally and find empirically good points for the most important sizes. We identify the main factors associated with good points. In addition, we explore other methods to reduce FP error, including mixed-precision convolution, and pairwise summation across DNN channels. Using our methods, we can significantly reduce FP error for a given block size, which allows larger block sizes to be used and reduced computation.

关键词： Floating point error numerical analysis winograd algorithm Toom-Cook algorithm convolution deep neural network

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WRA-SS: A High-Performance Accelerator Integrating winograd With Structured Sparsity for Convolutional Neural Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第1期32卷 164-177页

作者： Yang, Chen Meng, Yishuo Xi, Jiawei Xiang, Siwei Wang, Jianfei Mei, Kuizhi Xi An Jiao Tong Univ Sch Microelect Xian 710049 Shaanxi Peoples R China

Sparsification for convolutional neural networks (CNNs) and convolution acceleration algorithms such as the winograd algorithm are two efficient ways to reduce the intensive computations of existing CNNs. To better combine the sparsification and winograd algorithm, a close integration method is proposed to dynamically reduce the invalid parameters following the winograd transformation. To address the limitation of data bandwidth, a hierarchical two-level storage structure and corresponding data scheduling scheme are proposed, which can realize a conflict-free scheduling process. In addition, an algorithm hardware codesign method is proposed to efficiently and flexibly reduce the invalid computations led by the previous filter decomposition method. The accelerator is evaluated on Xilinx XCVU9P FPGA, reaching 412-MHz clock frequency. Compared to state-of-the-art designs, WRA-SS can achieve 1.54-5.33x and 1.17-7.39x performance improvement for VGG-16 under 80% weight sparsity and 0% weight sparsity, respectively.

关键词： Convolutional neural network data storage and schedule sparse neural network winograd algorithm

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