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FPGA-based system for artificial neural network arrhythmia classification

NEURAL COMPUTING & APPLICATIONS 2020年第8期32卷 4105-4120页

作者： Zairi, Hadjer Talha, Malika Kedir Meddah, Karim Slimane, Saliha Ould Univ Sci & Technol Houari Boumediene Dept Elect & Comp Sci BP 32 El Alia Algiers 16111 Algeria

The automatic detection and cardiac classification are essential tasks for real-time cardiac diseases diagnosis. In this context, this paper describes a field programmable gates array (FPGA) implementation of arrhythmia recognition system, based on artificial neural network. Firstly, we have developed an optimized software-based medical diagnostic approach, capable of defining the best electrocardiogram (ECG) signal classes. The main advantage of this approach is the significant features minimization, compared to the existing researches, which leads to minimize the FPGA prototype size and saving energy consumption. Secondly, to provide a continuous and mobile arrhythmia monitoring system for patients, we have performed a hardware implementation. The FPGA has been referred due to their easy testing and quick implementation. The optimized approach implementation has been designed on the Nexys4 Artix7 evaluation kit using the xilinx system generator for DSP. In order to evaluate the performance of our proposal system, the classification performances of proposed FPGA fixed point have been compared to those obtained from the MATLAB floating point. The proposed architecture is validated on FPGA to be a customized mobile ECG classifier for long-term real-time monitoring of patients.

关键词： Electrocardiogram Discrete wavelet transform Artificial neural network Multilayer perceptron xilinx system generator FPGA

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Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration

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IET SIGNAL PROCESSING 2020年第7期14卷 440-447页

作者： Sharma, Abhay Kumar Rawat, Tarun Agrawal, Anjali Univ Delhi Fac Technol New Delhi India

In this study, the design and field-programmable gate array (FPGA) implementation of the digital notch filter with the lattice wave digital filter (LWDF) structure is presented. For reducing the initial signal transient, the variable notch bandwidth filter is designed. During the initial samples, the notch filter has a wide bandwidth in order to diminish signal transient. As time moves forward, the notch bandwidth reduces to attain the possible minimum width. This results in minimised transient duration notch filter with a sufficiently high-quality factor. Previously, the IIR structure has been used for implementing the time varying bandwidth notch filter. Such a filter requires two variable coefficients for varying the notch width with time. The advantage of using a LWDF structure is that only one coefficient has variable values to vary the notch width with time. Therefore, the number of memory locations required to implement the proposed design is reduced by half. Moreover, the LWDF is less sensitive to the word-length effects. Thus, the proposed lattice wave digital notch filter (LWDNF) produces better results compared to the existing literature in terms of error analysis. The suggested LWDNF is then implemented on a field-programmable gate array using a xilinx system generator for the DSP design suite.

关键词： wave digital filters error analysis notch filters field programmable gate arrays logic design Q-factor minimal transient duration field-programmable gate array lattice wave digital filter structure signal transient variable notch bandwidth filter time-varying bandwidth notch filter notch width lattice wave digital notch filter FPGA quality factor infinite impulse response structure minimised transient duration error analysis field programmable gate array xilinx system generator DSP design suite

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Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking

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IEEE ACCESS 2020年 8卷 69072-69095页

作者： Das, Subhajit Sunaniya, Arun Kumar Maity, Reshmi Maity, Niladri Pratap Natl Inst Technol Dept Elect & Instrumentat Engn Silchar 788010 India Mizoram Univ Govt India Dept Elect & Commun Engn Tanhril 796004 India

This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding bit rate control based contrast mapping (EBCRCM) algorithm is proposed. An adaptive linear contrast mapping on pixel intensity value is asserted with RCM that controls the embedding bit rate without changing the embedding capacity to maintain distortion. xilinx system generator (XSG) and VIVADO tool construct the novel VLSI architecture that needs 173.362 ns latency for 100 MHz clock with throughput 46.146 Mbps and 5.8 ns critical path for single cycle of embedding process. The proposed algorithm is verified in MATLAB tool based software platform by taking different types of multimedia data like gray-scale images, color images and video signals. Implementation of low hardware resources based VLSI architecture through zed-board in real time field programmable gate array (FPGA) platform confirms the capability of high speed, low cost and real-time use. 100% agreement is observed from software simulations and hardware platforms.

关键词： Reversible image watermarking reversible contrast mapping xilinx system generator FPGA

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FPGA Hardware Co-Simulation of Image Encryption Using Stream Cipher Based on Chaotic Maps

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SENSING AND IMAGING 2020年第1期21卷 1-22页

作者： Hasan, Fadhil Sahib Saffo, Maryam Amer Mustansiriyah Univ Dept Elect Engn Baghdad Iraq Al Farabi Univ Coll Dept Comp Engn Baghdad Iraq

In this paper, new model of image encryption system using stream cipher based on fixed point chaotic maps are designed using xilinx system generator (XSG) in efficient way. Two Pseudo Random Bit generators (PRBGs) depends on chaotic maps are proposed that are Fixed Point XOR Chaotic Map-PRBG (FPXORCM-PRBG) and Fixed Point Cascade Chaotic Map-PRBG (FPCCM-PRBG). The randomness tests in the National Institute of Standards and Technology (NIST) are used to test the randomness measures of the proposed PRBGs. The security analysis, like histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPXORCM-PRBG and FPCCM-PRBG are suitable for image encryption based on stream cipher and outperforms some encryption algorithms.

关键词： Image encryption Chaotic maps Fixed point representation Stream cipher xilinx system generator FPGA hardware co-simulation

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Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization

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MICROPROCESSORS AND MICROsystemS 2021年 83卷 103732-103732页

作者： Das, Subhajit Sunaniya, Arun Kumar Maity, Reshmi Maity, Niladri Pratap Natl Inst Technol Dept Elect & Instrumentat Engn Silchar 788010 India Mizoram Univ Dept Elect & Commun Engn Aizawl 796004 India

This paper presents xilinx system generator (XSG) model design for realization of reversible watermarking algorithm using Difference Expansion (DE) approach in system-On-Chip (SoC) Field Programmable Gate Array (FPGA) environment. The reversible watermarking is verified by taking a (4 x 4) sized test image and is applicable for larger sizes of cover images. The outcomes of the result demonstrate that the proposed structural design allows combining MATLAB-Simulink and XSG during graphical user interface for image processing applications. The superiority of the algorithm is justified by using comparative analysis with some well-known methods in both software and hardware environments. The method provides effectively higher PSNR at higher embedding capacity. It is also found that the method requires less time and hardware resources with throughput of 13.516 Mb/s at operational frequency of 80 MHz for real time implementation using FPGA.

关键词： Watermarking SoC FPGA xilinx system generator Difference expansion Reversible watermarking

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xilinx Zynq FPGA for Hardware Implementation of a Chaos-Based Cryptosystem for Real-Time Image Protection

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JOURNAL OF CIRCUITS systemS AND COMPUTERS 2021年第11期30卷 2150204-2150204页

作者： Gafsi, Mohamed Abbassi, Nessrine Hajjaji, Mohammed Ali Malek, Jihene Mtibaa, Abdellatif Univ Monastir Lab Elect & Microelect LR99ES30 Monastir 5000 Tunisia Natl Sch Engineers Sousse Sousse 4054 Tunisia Higher Inst Appl Sci & Technol Sousse Sousse 4003 Tunisia

This paper proposes a well-optimized FPGA implementation of a chaos-based cryptosystem for real-time image encryption and decryption. A highly sensitive Pseudo-Random Number generator (PRNG) based on the Lorenz chaotic system is designed to generate pseudo-random numbers. A high-quality encryption key is acquired by encrypting the numbers of a 128-bit counter using the PRNG. For image encryption, the image is first decomposed into 128-bit blocks. Then, the blocks are encrypted by XORing pixels with the key stream. R cycles of encryption can be achieved to increase complexity. Finally, the blocks are concatenated to form an encrypted image. The algorithm is designed, implemented, and validated on the xilinx Zynq FPGA platform using the Vivado/system generator tool. The hardware design is well optimized for pipeline processing and low resource utilization. The experimental synthesis indicates that the provided architecture achieves high performance in terms of frequency and throughput. The encryption scheme is evaluated and analyzed by several tools and tests using different images. The experimental simulation results demonstrate that the hardware implementation is faster than a software implementation while maintaining the technique's effectiveness. The proposed hardware implementation is extremely adopted for secret image encryption and decryption that can be used in real-time applications.

关键词： Zynq FPGA xilinx system generator encryption chaos security level

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Implementation of PWM-based Direct Instantaneous Torque Control with Duty Cycle Interlock for a Switched Reluctance Machine 23

Implementation of PWM-based Direct Instantaneous Torque Cont...

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23rd International Conference on Electrical Machines and systems (ICEMS)

作者： von Hoegen, Anne Woerndle, Annegret De Doncker, Rik W. Rhein Westfal TH Aachen Inst Power Elect & Elect Drives Jaegerstr 17-19 D-52066 Aachen Germany

ISBN: (纸本)9784886864192

To obtain a constant output torque of switched reluctance machines (SRMs), direct instantaneous torque control (DITC) is a common method. There are several ways to modify and realize this algorithm. In this paper, we show the pulse width modulation (PWM) based DITC algorithm which is extended by a duty cycle interlock (DCI) that makes a compromise of minimizing both the resulting torque ripple and the switching losses of the inverter. Furthermore, the DCI guarantees phase overlap and consequently smooth torque at low speed. The control algorithm is realized on a programmable logic device (FPGA). The paper presents the chosen controller board's hardware topology as well as the key code segments that are graphically implemented in very high speed integrated circuit hardware description language (VHDL). The effects and advantages of the introduced DCI are investigated in simulation.

关键词： Switched Reluctance Drive Torque Control Duty Cycle Interlock xilinx system generator

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Improved torque performance in BLDC-motor-drive through Jaya optimization implemented on xilinx platform

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MICROPROCESSORS AND MICROsystemS 2021年 81卷 103681-103681页

作者： Prathibanandhi, K. Yaashuwanth, C. Basha, Adam Raja Saveetha Sch Engn Dept Elect & Elect Engn Chennai Tamil Nadu India Sri Venkateswara Coll Engn Dept Informat Technol Chennai Tamil Nadu India Audisankara Coll Engn & Technol Dept Elect & Commun Engn Gudur Andhra Pradesh India Audisankara Coll Engn & Technol Autonomous Gudur Dept Elect & Commun Engn Gudur Andhra Pradesh India

Robust dynamic speed response with less maintenance and efficient operation makes the Brushless Direct Current (BLDC) motors as an oblivious choice for many motoring applications which needs instantaneous speed control while developing high torque. This paper proposes Jaya optimization Algorithm on xilinx platform for BLDC Motor and Fractional Order Proportional Integral Derivative controller to improve its efficiency through minimizing the ripples present in the Torque of the motor. The control strategy of torque controller works with the combinations of xilinx and optimization algorithms. In this proposed controller, the strategy of control is achieved after deriving the BLDC motor?s dynamic mode there after the electronic interaction with BLDC motor is enrooted with the Math lab/Simulink model while tactically utilizing xilinx tools for all kind of co-simulation in the same model. Initially the dynamic model of a BLDC motor drive is derived and the control topology is designed with the help of the proposed controller. The controlling mechanism established in this paper is effective and efficient in minimizing the ripples present in the torque of the motor. The proposed controller is utilized for possible low-cost and high-performance industrial applications. The results are obtained and analyzed with existing methodologies and it shows that the proposed technique outperforms the existing models.

关键词： Brushless Direct Current (BLDC) motor Torque ripple minimization Speed control Jaya Algorithm (JA) xilinx system generator

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CIC FOR DECIMATION AND INTERPOLATION USING xilinx system generator

CIC FOR DECIMATION AND INTERPOLATION USING XILINX SYSTEM GEN...

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International Conference on Communication and Signal Processing

作者： V Elamaran R Vaishnavi A Maxel Rozario Slitta Maria Joseph Aylwin Cherian Department of Electronics and Communication Engineering (ECE) School of Electrical and Electronic Engineering (SEEE) SASTRA University Thanjavur India. Department of ECE SEEE SASTRA University Thanjavur India. Department of ECE SRM University Kattankulathur India.

ISBN: (纸本)9781467348652

In this paper a Cascaded integrated comb (CIC) filter, an optimized class of linear filters such as FIR is implemented for digital up conversion (DUC) and digital down conversion (DDC) for efficient transmission and reception in multirate system. CIC filters are often used for the purpose of reducing sampling rate (decimation) and increasing sampling rate (interpolation). Our work is to show the efficiency of CIC filters over FIR filters in fixed point applications. Single stage CIC filter and multistage CIC filters for interpolation and decimation are realized. Here multirate filter design models for decimation and interpolation are developed using xilinx system generator. Also multirate filters are further improved by cascading various CIC filter stages.

关键词： CIC filter decimator FPGA interpolator xilinx system generator

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Control with high performances based DTC strategy: FPGA implementation and experimental validation

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EPE JOURNAL 2019年第2期29卷 82-98页

作者： Krim, Saber Gdaim, Soufien Mtibaa, Abdellatif Mimouni, Mohamed Faouzi Univ Monastir Natl Engn Sch Monastir Res Unit Ind Syst Study & Renewable Energy Monastir Tunisia Univ Monastir Fac Sci Lab Elect & Microelect Monastir Tunisia

This paper aims to improve the induction motor performances using a modified Direct Torque Control (DTC). The DTC is featured by its simple structure and fast dynamic response. Also, it does not require a speed sensor and it is less dependent on the motor parameters. However, the basic handicaps of this method are the torque ripples and the current distortions due to the presence of the hysteresis controllers. This paper aims;firstly, to replace the hysteresis controllers and the switching table by a fuzzy logic system in order to overcome these handicaps. Furthermore, the sampling frequency is another parameter which must be investigated to reduce the commutation losses and the harmonic stator current waves. The second purpose of this paper is to reduce the execution time using a Field Programmable Gate Array (FPGA). The FPGA is able to execute the Fuzzy DTC (FDTC) with a higher sampling frequency, thanks to its parallel processing relative to the Digital Signal Processor (DSP). The FDTC model is verified by simulation using system generator tool and validated by experimentation utilizing an FPGA Virtex 5. Thus, excellent performances at low processing time are obtained using the xilinx FPGA Virtex 5.

关键词： Direct torque control fuzzy logic system real time xilinx system generator Field Programmable Gate Array (FPGA)

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