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Evaluating the effectiveness of Bat optimization in an adaptive and energy-efficient network-on-chip routing framework

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2024年 188卷

作者： Reddy, B. Naresh Kumar Kumar, Aruru Sai Natl Inst Technol Dept Elect & Commun Engn Trichy Tamil Nadu India VNR Vignana Jyothi Inst Engn & Technol Dept ECE Hyderabad Telangana India

adaptive routing is effective in maintaining higher processor performance and avoids packets over minimal or non -minimal alternate routes without congestion for a multiprocessor system on chip. However, many systems cannot deal with the fact that sending packets over an alternative path rather than the shorter, fixed -priority route can result in packets arriving at the destination node out of order. This can occur if packets belonging to the same communication flow are adaptively routed through a different path. In real -world network systems, there are strategies and algorithms to efficiently handle out -of -order packets without requiring infinite memory. Techniques like buffering, sliding windows, and sequence number management are used to reorder packets while considering the practical constraints of available memory and processing power. The specific method used depends on the network protocol and the requirements of the application. In the proposed technique, a novel technique aimed at improving the performance of multiprocessor systems on chip by implementing adaptive routing based on the Bat algorithm. The framework employs 5 stage pipeline router, that completely gained and forward a packet at the perfect direction in an adaptive mode. Bat algorithm is used to enhance the performance, which can optimize route to transmit packets at the destination. A test was carried out on various NoC sizes (6 X 6 and 8 X 8) under multimedia benchmarks, compared with other related algorithms and implemented on Kintex-7 FPGA board. The outcomes of the simulation illustrate that the proposed algorithm reduces delay and improves the throughput over the other traditional adaptive algorithms.

关键词： NoC (Network on Chip) MPSoC (Multiprocessor system on Chip) FPGA Throughput and delay adaptive routing algorithms

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A novel congestion-aware routing algorithm with prediction in mesh-based networks-on-chip

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NANO COMMUNICATION NETWORKS 2020年 26卷 100322-100322页

作者： Akbar, R. Safaei, F. Shahid Behshti Univ Fac Comp Sci & Engn Tehran Iran

Increasing the number of processing cores in the networks-on-chip in recent years has made congestion one of the most important challenges in this field. One of the best ways to solve this problem, which has greater effectiveness and less overhead, is the use of congestion-aware routing algorithm. In this algorithm, when a packet is generated, a route is selected from the minimum routes based on the betweenness centrality, history of the previous packets' routes and the adaptivity degree. The packet tries to move as far as possible in the selected route, and in the event of extreme congestion, it can change its route for limited times and again selects a new route according to the same parameters. To be more in detail, this algorithm is a combination of deterministic and adaptive routings. In order to reduce the overhead, the adaptive routing algorithm uses only the neighboring data. The proposed routing algorithm has been compared with five different algorithms in terms of the average packet latency, power consumption and variance of the switch activities under real and synthetic traffics. In turn, the proposed algorithm has better performance through simulation experiments. (C) 2020 Elsevier B.V. All rights reserved.

关键词： Network-on-chip (NoC) adaptive routing algorithms Congestion control management Congestion information Load balancing

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A congestion-aware routing algorithm for mesh-based platform networks-on-chip

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MICROELECTRONICS JOURNAL 2021年 114卷 105145-105145页

作者： Taherkhani, N. Akbar, R. Safaei, F. Moudi, M. Islamic Azad Univ Qazvin Branch Fac Comp & Informat Technol Engn Qazvin Iran Shahid Beheshti Univ Fac Comp Sci & Engn Tehran Iran Univ Torbat Heydarieh Dept Comp Engn Torbat Heydarieh Razavi Khorasan Iran

In this paper we propose a new congestion-aware routing algorithm. At the First step, this algorithm splits NoC into a number of subnets. Then a global routing algorithm within each subnet and a local routing algorithm between subnets are applied for routing. This issue combines the advantages of local and global algorithms together. This algorithm reduces the average latency of the packets in the system without increasing the power of the system. In the experiment that was conducted under uniform, transpose, and bit-reversal traffics, we found that this algorithm would go into the saturation state later than DyAD, CATRA and ERCA algorithms. In all other three algorithms and also, at all injection rates, our proposed algorithm has reduced the delayed average of 41.1% compared to DyAD, 17.2% compared to CATRA and 9.9% compared to ERCA. In addition, under the SPLASH 2 traffic, we found that package latency has improved by 24%, 17%, and 7% compared to the three DyAD, CATRA and ERCA algorithms respectively.

关键词： Network-on-chip (NoC) adaptive routing algorithms Congestion control management Congestion information Load balancing

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A novel adaptive congestion-aware and load-balanced routing algorithm in networks-on-chip

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COMPUTERS & ELECTRICAL ENGINEERING 2018年 71卷 60-76页

作者： Khodadad, Ehsan Akbar, Reza Safaei, Farshad Kunseshian Part Co Tech Dept Zartorsht St Tehran Iran Shahid Beheshti Univ Fac Comp Sci & Engn Tehran *** Iran

Congestion-aware routing algorithms attempt to have more diversity in routes to be chosen and avoid congested areas in networks-on-chip. In this paper, a novel fully adaptive congestion-aware routing algorithm called zigzag routing algorithm (ZRA) along with a new load-balanced method is proposed. ZRA presents a new way for transmitting congestion information, which allows a better view on congestion compared to other algorithms. Furthermore, the load-balanced method recognizes a forbidden area in the network according to betweenness centrality parameter. Fortifying ZRA with this novel load-balanced scheme yields more improvement in performance compared with the previous work. On average, we have accomplished 20.8% and 12.4% improvement in SPLASH-2 benchmark in contrast to DyAD and CATRA algorithms, respectively. It can be claimed that the proposed routing scheme does not consume more power than DyAD and CATRA. Moreover, a new parameter is suggested for comparing load-balanced algorithms, called the variance of crossbar activity.

关键词： Network-on-chip (NoC) adaptive routing algorithms Congestion control management Congestion information Load balancing

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Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip

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MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 80-88页

作者： Tatas, Konstantinos Chrysostomou, Chrysostomos Frederick Univ Dept Comp Sci & Engn Nicosia Cyprus

This paper presents the hardware implementation of a generic fuzzy logic-based adaptive routing scheme for both buffered and bufferless Networks-on-Chip (NoC). The routing scheme considers the dynamic traffic load and power consumption on neighboring router links to select the output port of an incoming flit. Specifically, fuzzy logic control is used to build a simple, generic, and efficient nonlinear control law that dynamically calculates the input link cost. Basing the link cost on traffic load and power consumption and not on empty buffer slots, makes the proposed algorithm applicable to both buffered and bufferless NoCs. Hardware implementation in ASIC and FPGA technologies demonstrate that the hardware area overhead imposed by the fuzzy control logic is from minimal to negligible for practical flit sizes and scales excellently with network size. Furthermore, since the fuzzy control logic is not in the router critical path, it imposes no additional latency. Finally, we demonstrate the efficiency of the proposed routing scheme through simulative evaluation against representative conventional counterparts. (C) 2017 Elsevier B.V. All rights reserved.

关键词： NoC adaptive routing algorithms Fuzzy logic

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End-Point Congestion Filter for adaptive routing with Congestion-Insensitive Performance

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2016年第1期15卷 9-12页

作者： Gorgues, Miguel Flich, Jose Univ Politecn Valencia Dept Comp Architecture E-46022 Valencia Spain

Interconnection networks are a critical component in most modern systems nowadays. Both off-chip networks, in HPC systems, data centers, and cloud servers, and on-chip networks, in chip multiprocessors (CMPs) and multiprocessors system-on-chip (MPSoCs), play an increasing role as their performance is vital for the performance of the whole system. One of the key components of any interconnect is the routing algorithm, which steers packets through the network. adaptive routing algorithms have demonstrated their superior performance by maximizing network resources utilization. However, as systems increase in size (both in off-chip and on-chip), new problems emerge. One of them is congestion where traffic jams inside the network lead to low throughput and high packet latency, significantly impacting overall system performance. We propose a mechanism to eradicate this phenomena and to allow adaptive routing algorithms to achieve the expected performance even in the presence of congestion situations. End-Point Congestion Filter, EPC, detects congestion formed at the end-points of the network, and prevents the congestion from spreading through the network. Basically, EPC disables adaptivity in congested packets. Preliminary results for mid and high congestion situations show EPC is able to totally decouple congestion from routing.

关键词： adaptive routing algorithms congestion interconnects on-chip networks

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adaptive Networks-on-Chip routing with Fuzzy Logic Control 19

Adaptive Networks-on-Chip Routing with Fuzzy Logic Control

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19th Euromicro Conference on Digital System Design (DSD)

作者： Tatas, K. Chrysostomou, C. Frederick Univ Dept Comp Sci & Engn Nicosia Cyprus

ISBN: (纸本)9781509028160

This paper presents the hardware implementation (both ASIC and FPGA) of a fuzzy logic-based adaptive routing scheme for Network-on-Chip (NoC). The routing scheme takes into account the dynamic traffic load and power consumption on neighboring router links to select the output port of an incoming flit. Specifically, fuzzy logic control is used to build a simple, generic, and efficient nonlinear control law that dynamically calculates the input link cost. Basing the link cost on traffic load and power consumption and not on empty buffer slots, makes the proposed algorithm applicable to both buffered and bufferless NoCs. Hardware implementation in ASIC and FPGA technologies demonstrate that the hardware area overhead imposed by the fuzzy control logic is from minimal to negligible for practical flit sizes and scales excellently with network size. Furthermore, since the fuzzy control logic is not in the router critical path, it imposes no additional latency. Finally, we demonstrate the efficiency of the proposed routing scheme through simulative evaluation against representative conventional counterparts.

关键词： NoC adaptive routing algorithms Fuzzy Logic

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A generic adaptive path-based routing method for MPSoCs

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JOURNAL OF SYSTEMS ARCHITECTURE 2011年第1期57卷 109-120页

作者： Daneshtalab, Masoud Ebrahimi, Masoumeh Xu, Thomas Canhao Liljeberg, Pasi Tenhunen, Hannu Univ Turku Dept Informat Technol SF-20500 Turku Finland

Several unicast routing protocols have been presented for unicast traffic in MPSoCs. Exploiting the unicast routing algorithms for multicast traffic increases the likelihood of deadlock and congestion. In order to avoid deadlock for multicast traffic, the Hamiltonian path strategy was introduced. The traditional Hamiltonian path routing protocols supporting both unicast and multicast traffic are based on deterministic models, leading to lower performance. In this paper, we propose an adaptive routing protocol for both unicast and multicast traffic without using virtual channels. The proposed method maximizes the degree of adaptiveness of the routing functions which are based on the Hamiltonian path while guaranteeing deadlock freedom. Furthermore, both unicast and multicast aspects of the presented method have been widely investigated separately. Results obtained in both synthetic and real traffic models show that the proposed adaptive method for multicast and unicast aspects has lower latency and power dissipation compared to previously proposed path-based multicasting algorithms with negligible hardware overhead. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Network-on-Chip Unicast and multicast routing algorithms adaptive routing algorithms Hamiltonian path-based routing algorithms

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Exploring Congestion-Aware Methods for Distributing Traffic in On-Chip Networks

Exploring Congestion-Aware Methods for Distributing Traffic ...

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1st International Conference on Innovative Computing Technology

作者： Ebrahimi, Masoumeh Daneshtalab, Masoud Liljeberg, Pasi Plosila, Juha Tenhunen, Hannu

ISBN: (纸本)9783642273360;9783642273377

The performance of NoC is highly affected by the network congestion condition. Congestion in the network can increase the delay of packets to be routed between sources and destinations, so it should be avoided. The routing decision can be based on local or non-local congestion information. Methods based on local congestion condition are generally simple but they are unable to balance the traffic load efficiently. On the other hand, methods using non-local congestion information are more complex while providing better distribution of traffic over the network. In this paper, we explored several proposed locally and non-locally congestion-aware methods. Then we discussed about their advantages and disadvantages. Finally, we compared the methods with each other regarding the latency metric.

关键词： Networks-on-Chip Congestion adaptive routing algorithms

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Efficient congestion-aware selection method for on-chip networks

Efficient congestion-aware selection method for on-chip netw...

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International Workshop on Reconfigurable Communication-Centric Systems-On-Chip

作者： Ebrahimi, Masoumeh Daneshtalab, Masoud Liljeberg, Pasi Plosila, Juha Tenhunen, Hannu Department of Information Technology University of Turku Finland

ISBN: (纸本)9781457706424

The choice of routing algorithm can have a large impact on the performance of on-chip networks. As adaptive routing algorithms may return a set of output channels, a selection method (routing policy) is employed to choose the appropriate output channel from the given set. In this paper, we present a novel on-chip network structure to detect the local and non-local congested areas. Based on the presented structure, an efficient congestion-aware selection method is proposed to choose an output channel that allows a packet to be routed through a less congested area. © 2011 IEEE.

关键词： adaptive systems Algorithm design and analysis Benchmark testing Heuristic algorithms Oceans routing System-on-a-chip adaptive routing algorithms congestion-aware selection method network routing network-on-chip on-chip networks output channel routing policy selection method

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