In this paper, by modifying the well-known viterbi algorithm, an adaptiveviterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable g...
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In this paper, by modifying the well-known viterbi algorithm, an adaptiveviterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptiveviterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the uonadaptiveviterbi algorithm, with a negligible increase in the hardware.
Together with convolutional encoders, viterbidecoders are commonly used to provide an excellent probability of error correction in wireless transmission. The encoder constraint length k must be set at higher values t...
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Together with convolutional encoders, viterbidecoders are commonly used to provide an excellent probability of error correction in wireless transmission. The encoder constraint length k must be set at higher values to achieve an improved bit error rate. With the growth of the Internet of Things (IoT) in recent years, there is inevitable demand for low-power IoT applications. Unfortunately, an increase in the value of k causes the complexity of the algorithm to increase exponentially. Consequently, the viterbidecoder's power consumption will increase exponentially, which is a detriment to many wireless communication devices. Many of the viterbidecoder's reduced complexity decoding approaches discussed in the past concentrated on the particular level of algorithms and architectures. Most of the studies focused on the difficulty of the decoder's Add-Compare Select Unit (ACSU) repetitive processing. This paper analyzes many variations carried out in the ACSU of the viterbi algorithm. Several separate algorithms were compared and an approach to a combined algorithm was suggested. This paper offered an in-depth description of the reduced computation and its design for the proposed algorithm. Each algorithm and reduced complexity are compared with the conventional VD. The impact of power consumption is evaluated through the bit-error-rate (BER) vs Signal-to-Noise ratio (SNR), such that the proposed algorithm was found to have the best dB gain between 0 dB and 5 dB, indicating a significant power improvement over the other algorithms.
viterbidecoders are widely employed along with convolutional encoders to provide an excellent error correction probability in digital wireless transmissions. To achieve lower error rates, the constraint length (k) of...
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ISBN:
(纸本)9781538662885
viterbidecoders are widely employed along with convolutional encoders to provide an excellent error correction probability in digital wireless transmissions. To achieve lower error rates, the constraint length (k) of the encoder, has to be defined at higher values. However, higher (k) results in increasingly complex implementations of the viterbi algorithm. As a result, the power consumption of the viterbidecoder will increase exponentially which is to the disadvantage of many wireless communication devices. Many reduced complexity decoding techniques of the viterbidecoder presented in the past focused on algorithm and architecture specific levels. Most of the studies concentrated on the Add-Compare Select Unit (ACSU) of the decoder, due to its nature of repetitive processing;also add to the complexity of the process. This paper presents a review of several variations of the viterbi algorithm performed in the ACSU. The comparison was made among several different algorithms with the most optimal algorithm presented in this paper. A combined algorithm approach is proposed at the end of the review for future improvement.
Generally, the data transmitted over any communication channel is affected due to noise. So, for detecting and correcting the errors due to channel noise, encoding and decoding should be performed at the transmitter a...
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ISBN:
(纸本)9781479962723
Generally, the data transmitted over any communication channel is affected due to noise. So, for detecting and correcting the errors due to channel noise, encoding and decoding should be performed at the transmitter and receiver end respectively. The viterbi algorithm is used in many communication channels for decoding convolutional codes. Using VLSI technology, the system requires low power, less area and high speed constraints while designing. Because of different steps for designing viterbidecoder speed of designing is limited. In this paper, different kind of implementation of viterbidecoder along with their performance has been discussed.
The noise reduced disc and the advanced signal reproduction system with the asymmetry compensatory function enhance the disc capacity up to 19.8 GBytes per DVD size. The noise was reduced by applying Aluminum based mu...
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ISBN:
(纸本)0819437336
The noise reduced disc and the advanced signal reproduction system with the asymmetry compensatory function enhance the disc capacity up to 19.8 GBytes per DVD size. The noise was reduced by applying Aluminum based multi-component alloy for the reflective layer, moreover all the loops in the system accurately function even under the signal asymmetric condition by using the newly developed Error Feedback type PRML. The error rate characteristics versus disc tilts suggest that the ROM disc system has sufficient performance for the practical use.
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