This paper presents a probabilistic framework based on Bayesian theory for the performance prediction and selection of an optimal segmentation algorithm. The framework models the optimal algorithm selection process as...
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This paper presents a probabilistic framework based on Bayesian theory for the performance prediction and selection of an optimal segmentation algorithm. The framework models the optimal algorithm selection process as one that accounts for the information content of an input image as well as the behavioral properties of a particular candidate segmentation algorithm. The input image information content is measured in terms of image features while the candidate segmentation algorithm's behavioral characteristics are captured through the use of segmentation quality features. Gaussian probability distribution models are used to learn the required relationships between the extracted image and algorithm features and the framework tested on the Berkeley Segmentation Dataset using four candidate segmentation algorithms.
The paper describes techniques to improve parallel algorithm design and performance evaluation on multiprocessors constructed from off-the-shelf microprocessors. Parallel algorithms are characterized by a set of param...
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The paper describes techniques to improve parallel algorithm design and performance evaluation on multiprocessors constructed from off-the-shelf microprocessors. Parallel algorithms are characterized by a set of parameters, and this characterization is used to generate a synthetic parallel program whose performance is then simulated. A concurrent program, which takes the form of a collection of machine language program files, is simulated in a serial fashion by enforcing a one-step behaviour constraint. The multiprocessor configuration to be simulated is described by three user-supplied data files and a pair of network function calls. By combining characterization, synthetic code generation and simulation we present a unique and flexible methodology for insight into multiprocessor dynamic behaviour.
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