检索结果-内蒙古大学图书馆

mapping 3-d IIR digital filter onto systolic arrays

MULTIDIMENSIONAL SYSTEMS AND SIGNAL PROCESSING 1996年第1期7卷 7-26页

作者： ElGuibaly, F Tawfik, A Department of Electrical and Computer Engineering University of Victoria Victoria Canada

We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI implementation.

关键词： multidimensional digital filter algorithm mapping combinatorial geometry systolic array design digital filter design task scheduling processor assignment

来源：评论

学校读者我要写书评

暂无评论

Design of array processors for 2-D Discrete Fourier Transform

引用

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1997年第4期E80D卷 455-465页

作者： Peng, ST Sedukhin, I Sedukhin, S Department of Computer Software Distributed Parallel Processing Laboratory University of Aizu Aizu-Wakamatsu-shi. 965 -80 Japan RandD Group Hiwada Electronic Corporation (Pioneer Group) Fukushima-ken 969-13 Japan

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

关键词： algorithm mapping 2-dimensional discrete Fourier transform parallelprocessing systolic array processors VLSI architectures

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable baseband processing architecture for communication

引用

IET COMPUTERS AND DIGITAL TECHNIQUES 2011年第1期5卷 63-72页

作者： Lu, W. Q. Zhao, S. Zhou, X. F. Ren, J. Y. Sobelman, G. E. Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

关键词： hardware resource usage digital signal processor chips Performance evaluation and testing high-level language fast Fourier transform reconfigurable architectures Digital signal processing hardware generation finite impulse response filter Integral transforms system performance evaluation Digital signal processing chips Microprocessors and microcomputers baseband signal processing FIR filters software tools performance evaluation homogeneous control mechanism reconfigurable baseband processing architecture digital signal processing chips communication standards multicore architectures Filtering methods in signal processing Computer architecture algorithm mapping heterogeneous reconfigurable execution units fast Fourier transforms

来源：评论

学校读者我要写书评

暂无评论

Ring-connected trees: a multipurpose VLSI architecture for parallel processing

引用

MICROPROCESSORS AND MICROSYSTEMS 1998年第5期21卷 291-298页

作者： Basu, SK Dattagupta, J Dattagupta, R Banaras Hindu Univ Ctr Comp Varanasi 221005 Uttar Pradesh India Indian Stat Inst Adv Comp & Microelect Unit Calcutta 700035 W Bengal India Jadavpur Univ Dept Comp Engn & Sci Calcutta 700032 W Bengal India

In this paper we propose a new general purpose VLSI architecture called ring-connected trees (RCT) for parallel processing. RCT requires less hardware in terms of processing elements and connecting links compared to a mesh-of-tree of comparable size and its diameter is less than that of mesh. It requires less chip area, less maximum edge length and crossing number compared to those required by mesh-of-tree [I] [F.T. Leighton, Layout for the shuffle-exchange graph and lower bound techniques for VLSI, Ph.D. dissertation, Department of Mathematics, MIT, 1981] under the Grid model of Thompson [2] [C.D. Thompson, Area-time complexity for VLSI. Technical report, Division of Computer Science, University of California, Berkeley, CA, January 1984]. By using spare PEs and links, RCT is made to tolerate multiple faults. Suitability of this architecture for multipurpose applications is demonstrated by designing parallel version of algorithms for a number of common computational problems. This structure requires linear and sublinear time for these algorithms and this is quite reasonable considering the simpler nature of the architecture. (C) 1998 Published by Elsevier Science B.V.

关键词： multipurpose architecture parallel processing fault tolerance algorithm mapping

来源：评论

学校读者我要写书评

暂无评论

Impact of the memory interface structure in the memory-processor integrated architecture for computer vision

引用

JOURNAL OF SYSTEMS ARCHITECTURE 2000年第3期46卷 259-274页

作者： Kim, Y Han, TD Kim, SD Yonsei Univ Dept Comp Sci Seodaemun Ku Seoul 120749 South Korea

The memory-based processor array (MPA) was previously designed as an effective memory-processor integrated architecture. The MPA can be easily attached into any host system via memory interface. In this paper, the impact of the memory interface structure is analytically analyzed for computer vision tasks. An analytical model is constructed to describe the characteristics of the memory interface structure. Performance improvement for the memory interface model of the MPA system can be 6-40% for vision tasks consisting of sequential and data parallel tasks. mapping algorithms to implement convolution and connected component labeling on the MPA are also presented. The asymptotic time complexities of the algorithms are evaluated to verify the cost-effectiveness and the efficiency of the MPA system. (C) 2000 Elsevier Science B.V. All rights reserved.

关键词： memory-processor integration SIMD array analytical model computer vision algorithm mapping

来源：评论

学校读者我要写书评

暂无评论

Design Heuristics for mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers

引用

JOURNAL OF COMPUTERS 2009年第6期4卷 542-553页

作者： Rice, Justin L. Abed, Khalid H. Morris, Gerald R. Jackson State Univ Dept Comp Engn Jackson MS 39217 USA

Because of the increasing need to develop efficient high-speed computational kernels, researchers have been looking at various acceleration technologies. One approach is to use field programmable gate arrays (FPGAs) in conjunction with general purpose processors to form what are known as high performance reconfigurable computers (HPRCs). HPRCs have already been shown to work well for both fixed-point and integer calculations. Floating-point calculations are a different matter;obtaining speedups has been somewhat elusive. This article, after introducing the three primary HPRC development flows, takes a detailed look at "the three p's," which addresses the crucial relationship among performance, pipelining, and parallelism. It also examines "the FPGA design boundary," which addresses some of the heuristics that allow developers to determine which application modules can be mapped onto the FPGAs. These ideas are illustrated by way of a simple floating-point application that is mapped onto a contemporary HPRC. This article expands upon earlier work by including details on how to map customized intellectual property cores into an HPRC environment via a hybrid development flow.

关键词： high performance reconfigurable computer (HPRC) field programmable gate array (FPGA) algorithm mapping

来源：评论

学校读者我要写书评

暂无评论

An Implementation of Configurable SIMD Core on FPGA

An Implementation of Configurable SIMD Core on FPGA

引用

2nd International Conference on Measurement, Instrumentation and Automation (ICMIA 2013)

作者： Wang, Guang Gao, Yinsheng Xian Univ Arts & Sci Xian 710065 Peoples R China

ISBN: (纸本)9783037857519

In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.

关键词： Architecture Configurable algorithm mapping SIMD core

来源：评论

学校读者我要写书评

暂无评论

Constraint directed CAD tool for automatic latency-optimal implementation of 1-D and 2-D Fourier transforms

Constraint directed CAD tool for automatic latency-optimal i...

引用

Conference on Reconfigurable Technology - FPGAs and Reconfigurable Processors for Computing and Communications IV

作者： Nash, JG CENTAR (United States)

ISBN: (纸本)0819446467

A specialized CAD tool is described that will take a user's high level code description of a non-uniform affinely indexed algorithm and automatically generate abstract latency-optimal systolic arrays. Emphasis has been placed on ease of use and the ability to either force conformation to specific design criteria or perform unconstrained explorations. How such design goals are achieved is illustrated in the context of LU decomposition and the matrix Lyapunov equation. The tool is then used to generate new I-D and 2-D hardware efficient systolic arrays for the discreet Fourier transform that take advantage of the use of the radix-4 matrix decomposition.

关键词： signal and image processing FPGA CAD tool systolic DFT FFT parallel algorithm algorithm mapping

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of high speed and real-time SAR signal processing module based on TMS320C6678

Design and Implementation of high speed and real-time SAR si...

引用

International Conference on Mechatronics Engineering and Computing Technology (ICMECT)

作者： Feng, Yang Hu, Shanqing Li, Qing Long, Teng Beijing Inst Technol Radar Res Lab Beijing 100081 Peoples R China

ISBN: (纸本)9783038351153

In order to meet the requirements of high speed and real-time in SAR processing system, as well as breaking the bondage that traditional processing board is subject to the algorithm. This paper designs a generic mass storage real-time signal processing module with TI's latest multi-core DSP-TMS320C6678 based on OpenVPX high-speed serial bus standard. This module has standardized, modularized, reconfigurable characteristics. This paper discusses the design of this module and the implementation of typical parallel SAR imaging algorithm mapping on this module. This peocessing module has been applied in a variety of airborne SAR radar signal processing systems and fully validated its powerful processing ability and versatility.

关键词： SAR TMS320C6678 SRIO large-capacity cache algorithm mapping

来源：评论

学校读者我要写书评

暂无评论

Performance analysis of extended vector-scalar operations using reconfigurable computing

Performance analysis of extended vector-scalar operations us...

引用

1st ACS/IEEE International Conference on Computer Systems and Applications

作者： Damaj, I Diab, H Amer Univ Beirut Fac Engn & Architecture Dept Elect & Comp Engn Beirut Lebanon

ISBN: (纸本)0769511651

This paper maps a new application, namely vector-scalar operations, onto the M1 MorphoSys (from UCI) reconfigurable computing system. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For Instance, 2 algorithms on an 8x8 RC array M1 were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation.

关键词： algebraic functions algorithm mapping reconfigurable computing parallel processing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：